74LVC_LVCH2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 22 February 2013 24 of 29
NXP Semiconductors
74LVC2T45-Q100; 74LVCH2T45-Q100
Dual supply translating transceiver; 3-state
14.4 Enable times
Calculate the enable times for the 74LVC2T45-Q100; 74LVCH2T45-Q100 using the
following formulas:
• t
PZH
(DIR to A) = t
PLZ
(DIR to B) + t
PLH
(B to A)
• t
PZL
(DIR to A) = t
PHZ
(DIR to B) + t
PHL
(B to A)
• t
PZH
(DIR to B) = t
PLZ
(DIR to A) + t
PLH
(A to B)
• t
PZL
(DIR to B) = t
PHZ
(DIR to A) + t
PHL
(A to B)
In a bidirectional application, these enable times provide the maximum delay from the
time the DIR bit is switched until an output is expected. For example, if the
74LVC2T45-Q100; 74LVCH2T45-Q100 initially is transmitting from A to B, then the DIR
bit is switched, the B port of the device must be disabled before presenting it with an input.
After the B port has been disabled, an input signal applied to it appears on the
corresponding A port after the specified propagation delay.
