74LVC_LVCH2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 22 February 2013 23 of 29
NXP Semiconductors
74LVC2T45-Q100; 74LVCH2T45-Q100
Dual supply translating transceiver; 3-state
Table 17 provides a sequence that illustrates data transmission from system-1 to
system-2 and then from system-2 to system-1.
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
14.3 Power-up considerations
The device is designed such that no special power-up sequence is required other than
GND being applied first.
Pull-up or pull-down only needed for 74LVC2T45-Q100.
Fig 14. Bidirectional logic level-shifting application
DDD
38//83'2:1
V\VWHP
9
&&$
$
$
*1'
9
&&%
%
%
',5
/9&74
/9&+74
38//83'2:1,2
',5&75/
9
&&
,2
',5&75/
9
&&
9
&&
9
&&
V\VWHP
Table 17. Description of bidirectional logic level-shifting application
[1]
State DIR CTRL I/O-1 I/O-2 Description
1 H output input system-1 data to system-2
2 H Z Z system-2 is getting ready to send data to system-1. I/O-1 and I/O-2
are disabled. The bus-line state depends on bus hold
3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 are still disabled. The bus-line
state depends on bus hold
4 L input output system-2 data to system-1
Table 18. Typical total supply current (I
CC(A)
+ I
CC(B)
)
V
CC(A)
V
CC(B)
Unit
0 V 1.8 V 2.5 V 3.3 V 5.0 V
0 V0 < 1< 1< 1< 1A
1.8 V < 1 < 2 < 2 < 2 2 A
2.5 V < 1 < 2 < 2 < 2 < 2 A
3.3 V < 1 < 2 < 2 < 2 < 2 A
5.0 V < 1 2 < 2 < 2 < 2 A
