contents of the specified address are shifted out serially on the DATA1 pin, beginning
with the MSB. When reading back data programmed from a Raw Programming Data
File (.rpd), the content is shifted out serially beginning with the LSB. Each data bit is
shifted out on the falling edge of the DCLK signal. The maximum DCLK frequency
during the read bytes operation is 50 MHz.
Figure 11. Read Bytes Operation Timing Diagram
nCS
DCLK
DATA0
DATA1
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
Operation Code (03h) 32-Bit Address
31 30 29 3 2 1 0
7 76 5 4 3 2 1 0
MSB
MSB
High Impedance
DATA Out 1 DATA Out 2
The first byte address can be at any location. The device automatically increases the
address to the next higher address after shifting out each byte of data. When the
device reaches the highest address, the address counter restarts at the beginning of
the same die, allowing the memory contents to be read out indefinitely until the read
bytes operation is terminated by driving the nCS signal high. A complete device
reading is done by executing the read operation:
• two times for EPCQ-L512 devices
• four times for EPCQ-L1024 devices
If the read bytes operation is shifted in while a write or erase cycle is in progress, the
operation is not executed and does not affect the write or erase cycle in progress.
Fast Read Operation (Bh)
When you execute the fast read operation, you first shift in the fast read operation
code, followed by a 4-byte addressing mode (A[31..0]), and dummy cycle(s) with
each bit being latched-in during the rising edge of the DCLK signal. Then, the memory
contents at that address is shifted out on DATA1 with each bit being shifted out at a
maximum frequency of 100 MHz during the falling edge of the DCLK signal.
EPCQ-L Serial Configuration Devices Datasheet
CF52013 | 2018.05.18
EPCQ-L Serial Configuration Devices Datasheet
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