OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

EPCQL256F24IN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
Figure 16. Extended Quad Input Fast Write Bytes Operation Sequence
DATA0
nCS
Operation Code (12h)
Don’t Care
MSB
DATA2
Don’t Care
‘1’
Data In
2 3 4 5 6 7 8 9
10 11 12
10
DCLK
2219
20
21
13 14
15
16
17
18
24
23
25
27
26
28
MSB
MSBMSB
MSB
MSB
32-Bit Address
Data In Data In
2
1 3 4
5
6
29
28 24 20 16
21 17
22 18
23 19
0 4
4 0
12
8
13
14
15
9
10
11
4
0
4
0
4
0
4 40
0 4
0
2 6
6 2
6
2
6
2
6
2
6 62
2 6
2
1 5
5 1
5
1
5
1
5
1
5 51
1 5
1
29 25
30 26
31 27
3 7
7 3
7
3
7
3
7
3
7 73
3 7
3
7
MSB
DATA3
DATA1
Erase Bulk Operation (C7h)
This operation sets all the memory bits to 1or 0xFF. Similar to the write bytes
operation, you must execute the write enable operation before the erase bulk
operation.
If you are using the EPCQ-L256 device and wish to erase the whole memory of your
device, you cannot use the erase die operation and instead must execute the erase
bulk operation.
You can implement the erase bulk operation by driving the nCS signal low and then
shifting in the erase bulk operation code on the DATA0 pin. The nCS signal must be
driven high after the eighth bit of the erase bulk operation code has been latched in.
Figure 17. Erase Bulk Operation Timing Diagram
Operation Code (C7h)
DATA0
nCS
DCLK
0 1 2 3 4 5 6 7
The device initiates a self-timed erase bulk cycle immediately after the nCS signal is
driven high. For details about the self-timed erase bulk cycle time, refer to t
WB
in Table
26 on page 30.
You must account for this delay before accessing the memory contents. Alternatively,
you can check the write in progress bit in the status register by executing the read
status operation while the self-timed erase cycle is in progress. The write in progress
bit is set to 1 during the self-timed erase cycle and 0 when it is complete. The write
enable latch bit in the status register is reset to 0 before the erase cycle is complete.
EPCQ-L Serial Configuration Devices Datasheet
CF52013 | 2018.05.18
EPCQ-L Serial Configuration Devices Datasheet
28
Erase Die Operation (C4h)
This operation sets all the memory bits of a particular die in an EPCQ-L512 or EPCQ-
L1024 device to 1 or 0xFF. Similar to the write bytes operation, you must execute the
write enable operation before the erase die operation.
If you are using the EPCQ-L512 or EPCQ-L1024 device, you must execute the erase
die operation to erase the memory of your device. You need to issue the erase die
operation for each die in your device. For example, you need to issue the erase die
operation twice for the EPCQ-L512 device and four times for the EPCQ-L1024 device.
EPCQ-L512 and EPCQ-L1024 devices have more than one die per device.
You can implement the erase die operation by driving the nCS signal low and then
shifting in the erase die operation code on the DATA0 pin, followed by the address
bytes, any address within the single 256 Mb die is valid. The nCS signal must be
driven high after the eighth bit of the erase die operation code has been latched in.
Erase Sector Operation (D8h)
The erase sector operation allows you to erase a certain sector in the EPCQ-L device
by setting all the bits inside the sector to 1 or 0xFF. This operation is useful if you
want to access the unused sectors as a general purpose memory in your applications.
You must execute the write enable operation before the erase sector operation.
When you execute the erase sector operation, you must first shift in the erase sector
operation code, followed by the 4-byte addressing mode (A[31..0]) of the chosen
sector on the DATA0 pin. The 4-byte addressing mode for the erase sector operation
can be any address inside the specified sector. For details about the sector address
range, refer to Table 11 on page 9 through Table 13 on page 10. Drive the nCS signal
high after the eighth bit of the erase sector operation code has been latched in.
Figure 18. Erase Sector Operation Timing Diagram
DATA0
Operation Code (D8h) 32-Bit Address
nCS
DCLK
0 1 2 3 4 5 6 7 8 9 36 37 38 39
3 2 1 031 30
MSB
The device initiates a self-timed erase sector cycle immediately after the nCS signal is
driven high. For details about the self-timed erase sector cycle time, refer to t
ES
in
Table 26 on page 30. You must account for this amount of delay before another page
of memory is written. Alternatively, you can check the write in progress bit in the
status register by executing the read status operation while the self-timed erase cycle
is in progress. The write in progress bit is set to 1 during the self-timed erase cycle
and 0 when it is complete. The write enable latch bit in the status register is set to 0
before the self-timed erase cycle is complete.
EPCQ-L Serial Configuration Devices Datasheet
CF52013 | 2018.05.18
EPCQ-L Serial Configuration Devices Datasheet
29
Power Mode
EPCQ-L devices support active and standby power modes. When the nCS signal is low,
the device is enabled and is in active power mode. The FPGA is configured while the
EPCQ-L device is in active power mode. When the nCS signal is high, the device is
disabled but remains in active power mode until all internal cycles are completed, such
as write or erase operations. The EPCQ-L device then goes into standby power mode.
The I
CC1
and I
CC0
parameters list the V
CC
supply current when the device is in active
and standby power modes. Refer to Table 5 on page 5.
Timing Information
Write Operation Timing
Figure 19. Write Operation Timing Diagram
DATA0
nCS
DCLK
DATA
t
NCSH
t
NCSSU
t
DSU
t
DH
t
CL
t
CH
t
CSH
Bit n Bit n - 1 Bit 0
High Impedance
Table 26. Write Operation Timing Parameters
Symbol Parameter Min Typical Max Unit
f
WCLK
Write clock frequency (from the FPGA,
download cable, or embedded processor) for
write enable, write disable, read status, read
device identification, write bytes, erase bulk,
erase die, and erase sector operations
— — 100 MHz
t
CH
DCLK high time
4 — — ns
t
CL
DCLK low time
4 — — ns
t
NCSSU
Chip select (nCS) setup time
4 — — ns
t
NCSH
Chip select (nCS) hold time
4 — — ns
t
DSU
DATA[] in setup time before the rising edge on
DCLK
2 — — ns
t
DH
DATA[] hold time after the rising edge on
DCLK
3 — — ns
t
CSH
Chip select (nCS) high time
50 — — ns
t
WB
Write bytes cycle time — 0.6 5 ms
t
WS
Write status cycle time — 1.3 8 ms
t
EB
Erase bulk cycle time for EPCQ-L256 — 240 480 s
continued...
EPCQ-L Serial Configuration Devices Datasheet
CF52013 | 2018.05.18
EPCQ-L Serial Configuration Devices Datasheet
30
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

EPCQL256F24IN

Mfr. #:
Buy EPCQL256F24IN
Manufacturer:
Intel / Altera
Description:
FPGA - Configuration Memory
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet