3-Phase Power MOSFET Controller for Automotive Applications
A3935
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ELECTRICAL CHARACTERISTICS (continued) at T
J
= –40°C to 150°C, V
BAT
= 7 to 16 V, V
DD
= 4.75 to 5.25 V,
ENABLE = 22.5 kHz, 50% duty cycle, two phases active;unless otherwise noted
Characteristics Symbol Conditions Min. Typ
1
. Max. Units
Gate Drives, GLx (internal sink or lower switch stages)
6
Sink Current (pulsed) I
xL
V
DSL
= 10 V, T
J
= 25°C – 850 – mA
V
DSL
= 10 V, T
J
= 135°C 550 – – mA
Sink On Resistance r
DSL(on)
I
xL
= 150 mA, T
J
= 25°C 1.8 – 6.0 Ω
I
xL
= 150 mA, T
J
= 135°C 3.0 – 7.5 Ω
Gate Drives, GHx, GLx (General)
5,6
Propagation Delay, Logic only t
pd
Logic input to unloaded GHx, GLx – – 150 ns
Output Skew Time t
sk(o)
Grouped by edge, phase–to–phase – – 50 ns
Dead Time (shoot–through prevention) t
dead
Between GHx, GLx transitions of same phase 75 – 180 ns
Sense Amplifier
Input Bias Current
2
I
bias
CSP = CSN = 0 V –180 – –360 μA
Input Offset Current
2
I
IO
CSP = CSN = 0 V – – ±35 μA
Input Resistance r
i
CSP with respect to GND – 80 – kΩ
CSN with respect to GND – 4.0 – kΩ
Diff. Input Operating Voltage V
ID
V
ID
= CSP – CSN, –1.3V < CSP,N < 4V – – ±200 mV
Output Offset Voltage V
OO
CSP = CSN = 0 V 77 250 450 mV
Output Offset Voltage Drift ΔV
OO
CSP = CSN = 0 V – 100 – μV/°C
Input Common Mode Operating Range V
IC
CSP = CSN –1.5 – 4.0 V
Voltage Gain A
V
V
ID
= 40 to 200 mV 18.6 19.2 19.8 V/V
Low Output Voltage Error E
V
V
ID
= 0 to 40 mV, V
O
= (19.2 × V
ID
) + V
O
+ E
v
– – ±25 mV
DC Common Mode Attenuation A
VC
CSP = CSN = 200 mV 28 – – dB
Output Resistance r
O
V
CSOUT
= 2.0 V – 8.0 – Ω
Output Dynamic Range V
CSOUT
I
CSOUT
= –100 μA at top rail, 100 μA at bottom rail 0.075 –
V
DD
–
0.25
V
Output Current, Sink I
sink
V
CSOUT
= 2.5 V 20 – – mA
Output Current, Source
2
I
source
V
CSOUT
= 2.5 V –1.0 – – mA
VDD Supply Ripple Rejection PSRR
VDD
CSP = CSN = GND, frequency = 0 to 1 MHz 20 – – dB
VREG Supply Ripple Rejection PSRR
VREG
CSP = CSN = GND, frequency = 0 to 300 kHz 45 – – dB
Small Signal 3 dB Bandwidth BW
f3db
10 mV input – 1.6 – MHz
AC Common Mode Attenuation A
VC(ac)
V
cm
= 250 mV(pp), frequency = 0 to 800 kHz 26 – – dB
Output Slew Rate (positive or negative) SR 200 mV step input, measured at 10/90% points 10 – – V/μs
Fault Logic
VDD Undervoltage V
DD(uv)
Decreasing V
DD
3.8 – 4.3 V
VDD Undervoltage Hysteresis ∆V
DD(uv)
V
DD(recovery)
– V
DD(uv)
100 – 300 mV
OVSET Operating Voltage Range V
SET(ov)
0–V
DD
V
OVSET Calibrated Voltage Range V
SET(ov)cal
0 – 2.5 V
OVSET Input Current Range
2
I
SET(ov)
–1.0 – 1.0 μA
VBAT Overvoltage Range V
BAT(ov)
0 V < V
SET(ov)
< 2.5 V 19.4 – 40 V
Increasing V
BAT
, V
SET(ov)
= 0 V 19.4 22.4 25.4 V
VBAT Overvoltage Hysteresis ∆V
BAT(ov)
Percent of V
BAT(ov)
value set by V
SET(ov)
9.0 – 15 %
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