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A3935KLQ-T

P1-P3P4-P6P7-P9P10-P12P13-P13
3-Phase Power MOSFET Controller for Automotive Applications
A3935
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance R
θJA
On 4-layer PCB, based on JEDEC standard 44 ºC/W
*Additional thermal information available on Allegro Web site.
Thermal Characteristics
50 75 100 125 15025
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN °C
5.0
0
1.0
2.0
3.0
4.0
R
θJA
= 44°C/W*
Power Dissipation versus Ambient Temperature
3-Phase Power MOSFET Controller for Automotive Applications
A3935
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Terminal Descriptions
AHI, BHI, and CHI. Direct control of high-side gate outputs
GHA, GHB, and GHC. Logic 1 drives the gate on. Logic 0 pulls
the gate down, turning off the external power MOSFET. Inter-
nally pulled down when the terminal is open.
ALO, BLO, and CLO. Direct control of low-side gate outputs
GHA, GHB, and GHC. Logic 1 drives the gate on. Logic 0 pulls
the gate down, turning off the external power MOSFET. Inter-
nally pulled down when the terminal is open.
BOOSTD. Boost converter switch drain connection.
BOOSTS. Boost converter switch source connection.
CA, CB, and CC. High-side connection for the bootstrap
capacitors, CBOOTx, positive supply for high-side gate drive.
The bootstrap capacitor is charged to V
REG
when the output Sx
terminal is low. When the output swings high, the voltage on this
terminal rises with the output to provide the boosted gate voltage
needed for N-channel power MOSFETs.
CSN. Input for current-sense differential amplifier, on the
inverting, negative side. Kelvin connection for the ground side of
the current-sense resistor, RSENSE.
CSOUT. Amplifier output voltage proportional to the current
sensed across an external low-value resistor placed in the ground
side of the power MOSFET bridge.
CSP. Input for current-sense differential amplifier, on the non-
inverting, positive side. Connected to the positive side of the
sense resistor, RSENSE.
ENABLE. Logic 0 disables the gate control signals and switches
off all the gate drivers (low) causing a coast condition. Can be
used in conjunction with the gate inputs to PWM (pulse wave
modulate) the load current. Internally pulled down when the
terminal is open.
¯F¯ ¯A¯ ¯U¯ ¯L¯ ¯T¯ . Diagnostic logic output signal. When low, indicates
that one or more fault conditions have occurred.
GHA, GHB, and GHC. High-side gate drive outputs for
N-channel MOSFET drivers. External series gate resistors can
control the slew rate seen at the power driver gate, thereby
controlling the di/dt and dv/dt of Sx outputs.
GLA, GLB, and GLC. Low-side gate drive outputs for external,
N-channel MOSFET drivers. External series gate resistors can
control slew rate.
GND. Ground, or negative, side of VDD and VBAT supplies.
LSS. Low-side gate driver return. Connects to the common
sources on the low sides of the power MOSFET bridge.
OVFLT. Logic 1 indicates that the V
BAT
level exceeded the
VBAT overvoltage trip point set by the OVSET level. It will
recover after exceeding a hysteresis below that maximum value.
Normally, it has a high-impedance state. If OVFLT and UVFLT
are both in high-impedance state; then, at least, a thermal
shutdown or VDD undervoltage has occurred.
OVSET. A positive dc level that controls the VBAT overvoltage
trip point. Usually, set by a precision resistor divider network
between VDD and GND, but can be held grounded for a preset
value. When this terminal is open, it sets an unspecified but high
overvoltage trip point.
SA, SB, and SC. Directly connected to the motor terminals,
these terminals sense the voltages switched across the load and
are connected to the negative side of the bootstrap capacitors,
CBOOTx. Also, are the negative supply connection for the
floating high-side drivers.
UVFLT. Logic 1 indicates that the V
BAT
level is below its
minimum value. It will recover after exceeding a hysteresis above
that minimum value. Has a high-impedance state. If UVFLT and
OVFLT are both in high-impedance state; then, at least, a thermal
shutdown or VDD undervoltage has occurred.
VBAT. Battery voltage. Positive input. usually connected to the
motor voltage supply.
VBOOST. Boost converter output, 16 V nominal, is also the
input to the regulator for VREG. Has internal boost-current
and boost-voltage control loops. In high-voltage systems is
approximately one diode drop below V
BAT
.
VDD. Logic supply, +5 V nominal.
VDRAIN. Kelvin connection for drain-to-source voltage monitor.
Connected to the high-side drains of the MOSFET bridge. High
impedance when this terminal is open, and registers as a short-to-
ground fault on all motor phases.
VDSTH. A positive dc level that sets the drain-to-source monitor
threshold voltage. Internally pulled down when this terminal is
open.
VREG. High-side gate driver supply, 13.5 V nominal. Has low-
voltage dropout (LDO) feature.
3-Phase Power MOSFET Controller for Automotive Applications
A3935
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Motor Lead Protection. A fault detection circuit monitors
the voltage across the drain-to-source of the external MOSFETs.
A fault is asserted low on the output terminal, ¯F¯ ¯A¯ ¯U¯ ¯L¯ ¯T¯ , if the
drain-to-source voltage of any MOSFET that is instructed to
turn on is greater than the voltage applied to the V
DSTH
input
terminal. When a high-side switch is turned on, the voltage from
V
DRAIN
to the appropriate motor phase output, V
SX
, is examined.
If the motor lead is shorted to ground before the high-side is
turned on, the measured voltage will exceed the threshold and
the ¯F¯ ¯A¯ ¯U¯ ¯L¯ ¯T¯ terminal will go low. Similarly, when a low-side
MOSFET is turned on, the differential voltage between the motor
phase (drain) and the LSS terminal (source) is monitored. V
DSTH
is set by a resistor divider to V
DD
.
The V
DRAIN
is intended to be a Kelvin connection for the
high-side, drain-to-source monitor circuit. Voltage drops across
the power bus are eliminated by connecting an isolated PCB trace
from the V
DRAIN
terminal to the drain of the MOSFET bridge.
This allows improved accuracy in setting the V
DSTH
threshold
voltage. The low-side, drain-to-source monitor uses the LSS
terminal, rather than V
DRAIN
, for comparison with V
DSTH
.
The A3935 just reports these motor faults.
Fault Outputs. Transient faults on any of the fault outputs
are to be expected during switching, and will not disable the
gate drive outputs. External circuitry or controller logic must
determine if the faults represent a hazardous condition.
¯F¯ ¯A¯ ¯U¯ ¯L¯ ¯T¯ . This terminal will go active low when any of the follow-
ing conditions occur:
• V
BAT
overvoltage
• V
BAT
undervoltage
• V
REG
undervoltage
• Motor lead short-to-ground
• Motor lead short-to-supply
or short-to-battery
• Bridge (or V
DRAIN
) open
• V
DD
undervoltage
• Thermal shut down
OVFLT. Asserts high when a V
BAT
overvoltage fault occurs and
resets low after a recovery hysteresis. It has a high-impedance
state when a thermal shutdown or V
DD
undervoltage occurs. The
voltage at the OVSET terminal, V
OVSET
, controls the V
BAT
over-
voltage set point V
BAT(ov)
, as follows:
V
BAT(ov)
= (A
BAT(ov)
× V
SET(ov)
) + V
BAT(ov)(0)
,
where A
BAT(ov)
is the gain (12) and V
BAT(ov)(0)
is the value of
V
BAT(ov)
when V
SET(ov)
= 0 (V
BAT(ov)
≈ 22.4). For the above
formula to be valid, all variables must be in range and below the
maximum operating specification.
UVFLT. Asserts high when a V
BAT
undervoltage fault occurs and
resets low after exceeding a recovery hysteresis. It has a high-
impedance state when a thermal shut down or V
DD
undervoltage
occurs. OVFLT and UVFLT are mutually exclusive by definition.
Current Sensing. A current-sense amplifier is provided to
allow system monitoring of the load current. The differential
amplifier inputs are intended to be Kelvin-connected across a
low-value sense resistor or current shunt. The output voltage is
represented by:
V
CSOUT
= ( I
LOAD
×A
V
× R
SENSE
) + V
OS
where V
OS
is the output voltage calibrated at zero load current
and A
V
is the differential amplifier gain of about 19.2. If either
the CSP or CSN pin is open, the CSOUT pin will go to its
maximum positive level.
Shut Down. If a fault occurs because of excessive junction
temperature or undervoltage on V
DD
or V
BAT
, all gate driver
outputs are driven low until the fault condition is removed. In
addition, the boost supply switch and VREG are turned off until
those undervoltages and junction temperatures recover.
Boost Supply. V
BOOST
is controlled by an inner current-
control loop, and by an outer voltage-feedback loop. The
current-control loop turns off the boost switch for 5 μs whenever
the voltage across the boost current-sense resistor exceeds
500 mV. A diode reverse-recovery current flows through the
sense resistor whenever the boost switch turns on, which could
result in turning off the switch again if not for the blanking-time
circuit. Adjustment of this external sense resistor determines the
maximum current in the inductor. Whenever V
BOOST
exceeds the
predefined threshold, 16 V nominal the boost switch is inhibited.
Functional Description
P1-P3P4-P6P7-P9P10-P12P13-P13

A3935KLQ-T

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IC MOTOR DRVR 4.75V-5.25V 36QSOP
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