AD5532
Rev. D | Page 9 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
00939-C-028
A
B
C
D
E
F
G
H
J
K
L
A
1234567891011
1234567891011
B
C
D
E
F
G
H
J
K
L
TOP VIEW
Figure 7. 74-Lead CSPBGA Ball Configuration
Table 6. 74-Lead CSPBGA Ball Configuration
CSPBGA Number Ball Name CSPBGA Number Ball Name CSPBGA Number Ball Name
A1 Not connected C10 AV
CC
1 J10 VO9
A2 A4 C11 REF_OUT J11 VO11
A3 A2 D1 VO20 K1
VO17
A4 A0 D2 DAC_GND2 K2
VO15
A5
CS/SYNC
D10 AV
CC
2 K3 VO27
A6 DV
CC
D11 OFFS_OUT K4 V
SS
3
A7 SCLK E1 VO26 K5
V
SS
1
A8 OFFSET_SEL E2 VO14 K6
V
SS
4
A9
BUSY
E10 AGND1 K7
V
DD
2
A10
TRACK
/RESET
E11 OFFS_IN K8
VO2
A11 Not connected F1 VO25 K9
VO10
B1 VO16 F2 VO21 K10
VO13
B2 Not connected F10 AGND2 K11
VO12
B3 A3 F11 VO6 L1
Not connected
B4 A1 G1 VO24 L2
VO28
B5
WR
G2 VO8 L3
VO29
B6 DGND G10 VO5 L4
VO30
B7 D
IN
G11 VO3 L5 V
DD
3
B8 CAL H1 VO23 L6
V
DD
1
B9
SER/PAR
H2 VIN L7
V
DD
4
B10 DOUT H10 VO4 L8
VO31
B11 REF_IN H11 VO7 L9
VO0
C1 VO18 J1 VO22 L10
VO1
C2 DAC_GND1 J2 VO19 L11
Not connected
C6 Not connected J6 V
SS
2
AD5532
Rev. D | Page 10 of 20
Table 7. Pin Function Descriptions
Pin Function
AGND (1–2) Analog GND pins.
AV
CC
(1–2) Analog Supply pins. Voltage range from 4.75 V to 5.25 V.
V
DD
(1–4) V
DD
Supply pins. Voltage range from 8 V to 16.5 V.
V
SS
(1–4) V
SS
Supply pins. Voltage range from –4.75 V to –16.5 V.
DGND Digital GND pins.
DV
CC
Digital Supply pins. Voltage range from 2.7 V to 5.25 V.
DAC_GND (1–2) Reference GND supply for all DACs.
REF_IN Reference voltage for Channels 0–31.
REF_OUT Reference Output Voltage.
V
OUT
(0–31) Analog Output Voltages from the 32 channels.
V
IN
Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
A4–A1, A0
Parallel Interface: 5 address pins for 32 channels. A4 = MSB of channel address. A0 = LSB. Internal pull-up devices on these
logic inputs. Therefore, they can be left floating and default to a logic high condition.
CAL
Parallel Interface: Control input that allows all 32 channels to acquire V
IN
simultaneously. Internal pull-down devices on
these logic inputs. Therefore, they can be left floating and default to a logic low condition
CS
/SYNC
This is the active low Chip Select pin for the parallel interface and the Frame Synchronization pin for the serial interface.
WR
Parallel interface: Write pin; active low. This is used in conjunction with the CS pin to address the device using the parallel
interface. Internal pull-down devices on these logic inputs. Therefore, they can be left floating and default to a logic low
condition.
OFFSET_SEL
Parallel interface: Offset Select pin; active high. This is used to select the offset channel. Internal pull-down devices on
these logic inputs. Therefore, they can be left floating and default to a logic low condition
SCLK Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in ISHA mode).
D
IN
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK. Internal pull-up devices on these logic
inputs. Therefore, they can be left floating and default to a logic high condition.
D
OUT
Output from the DAC registers for read back. Data is clocked out on the rising edge of SCLK and is valid on the falling
edge of SCLK.
SER/PAR
This pin allows the user to select whether the serial or parallel interface is used. If the pin is tied low, the parallel interface
is used. If it is tied high, the serial interface is used. Internal pull-down devices on these logic inputs. Therefore, they can
be left floating and default to a logic low condition.
OFFS_IN
Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to this pin if the
user wants to drive this pin with the offset channel.
OFFS_OUT Offset Output. This is the acquired/programmed offset voltage which can be tied to OFFS_IN to offset the span.
BUSY This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns high when
the acquisition operation is complete.
TRACK
/RESET If this input is held high, V
IN
is acquired once the channel is addressed. While it is held low, the input to the gain/offset
stage is switched directly to V
IN
. The addressed channel begins to acquire V
IN
on the rising edge of TRACK. See TRACK
Input section for further information. This input can also be used as a means of resetting the complete device to its
power-on-reset conditions. This is achieved by applying a low-going pulse of between 90 ns and 200 ns to this pin. See
section on RESET
Function for further details. Internal pull-up devices on these logic inputs. Therefore, they can be left
floating and default to a logic high condition.
00939-C-008
V
OUT
IDEAL
TRANSFER
FUNCTION
UPPER
DEAD BAND
LOWER
DEAD BAND
OFFSET
ERROR
ACTUAL
TRANSFER
FUNCTION
GAIN ERROR +
OFFSET ERROR
V
IN
2.96
3V
70mV
0V
00939-C-007
DAC CODE
0 16k
OUTPUT
VOLTAGE
IDEAL TRANSFER
FUNCTION
IDEAL GAIN
×
REFIN
IDEAL GAIN
×
50mV
FULL-SCALE
ERROR RANGE
OFFSET
RANGE
Figure 8. DAC Transfer Function (OFFS_IN=0)
Figure 9. ISHA Transfer Function
AD5532
Rev. D | Page 11 of 20
TERMINOLOGY
DAC MODE
Integral Nonlinearity (INL)
This is a measure of the maximum deviation from a straight
line passing through the endpoints of the DAC transfer
function. It is expressed as a percentage of full-scale span.
Differential Nonlinearity (DNL)
This is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
DNL of ±1 LSB maximum ensures monotonicity.
Offset
Offset is a measure of the output with all zeros loaded to the
DAC and OFFS_IN = 0. Because the DAC is lifted off the
ground by approximately 50 mV, this output is typically
mV50×= GainV
OUT
Full-Scale Error
This is a measure of the output error with all 1s loaded to the
DAC. It is expressed as a percentage of full-scale range. See
Figure 8. It is calculated as
(
)
REFINGainIdealVErrorScaleFull
ScaleFullOUT
×=
)(
where
25532ADfor7
5/3/15532ADfor52.3
=
=
GainIdeal
GainIdeal
Output Settling Time
This is the time taken from when the last data bit is clocked into
the DAC until the output has settled to within ±0.39%.
OFFS_IN Settling Time
The time taken from a 0 V to 3 V step change in input voltage
on OFFS_IN until the output has settled to within ±0.39%.
Digital-to-Analog Glitch Impulse
This is the area of the glitch injected into the analog output
when the code in the DAC register changes state. It is specified
as the area of the glitch in nV-secs when the digital code is
changed by 1 LSB at the major carry transition (011 . . . 11 to
100 . . . 00 or 100 . . . 00 to 011 . . . 11).
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale while a full-scale code change (all 1s to all 0s and
vice versa) is written to another DAC. It is expressed in nV-secs.
Analog Crosstalk
This is the area of the glitch transferred to the output (V
OUT
) of
one DAC due to a full-scale change in the output (V
OUT
) of
another DAC. The area of the glitch is expressed in nV-secs.
Digital Feedthrough
This is a measure of the impulse injected into the analog
outputs from the digital control inputs when the part is not
being written to, i.e.,
CS
/
SYNC
is high. It is specified in nV-secs
and is measured with a worst-case change on the digital input
pins, for example, from all 0s to all 1s and vice versa.
Output Noise Spectral Density
This is a measure of internally generated random noise.
Random noise is characterized as a spectral density (voltage per
root Hertz). It is measured by loading all DACs to midscale and
measuring noise at the output. It is measured in nV/(√
Hz
).
Output Temperature Coefficient
This is a measure of the change in analog output with changes
in temperature. It is expressed in ppm/°C.
DC Power-Supply Rejection Ratio (PSRR)
DC power-supply rejection ratio is a measure of the change in
analog output for a change in supply voltage (V
DD
and V
SS
). It is
expressed in dBs. V
DD
and V
SS
are varied ±5%.
DC Crosstalk
This is the DC change in the output level of one DAC at
midscale in response to a full-scale code change (all 0s to all 1s
and vice versa) and an output change of all other DACs. It is
expressed in μV.
ISHA MODE
V
IN
to V
OUT
Nonlinearity
The measure of the maximum deviation from a straight line
passing through the endpoints of the V
IN
versus V
OUT
transfer
function. It is expressed as a percentage of the full-scale span.
Offset Error
This is a measure of the output error when V
IN
= 70 mV. Ideally,
with V
IN
= 70 mV:
(
)
(
)
(
)
mV170
_ INOFFS
OUT
VGainGainV ×
×
=
Offset error is a measure of the difference between V
OUT
(actual)
and V
OUT
(ideal). It is expressed in mV and can be positive or
negative. See Figure 9.
Gain Error
This is a measure of the span error of the analog channel. It is
the deviation in slope of the transfer function expressed in mV.
See Figure 9. It is calculated as
Gain Error =
Actual Full-Scale Output Ideal Full-Scale Output Offset Error
where:
(
)
(
)
INOFFS
VGainGainOutputScaleFullIdeal
_
196.2
×
×=
AC Crosstalk
This is the area of the glitch that occurs on the output of one
channel while another channel is acquiring. It is expressed in
nV-secs.
Output Settling Time
This is the time taken from when
BUSY
goes high to when the
output has settled to ±0.018%.
Acquisition Time
This is the time taken for the V
IN
input to be acquired. It is the
length of time that
BUSY
stays low.

AD5532ABC-3

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 32 CH 14-BIT Bipolar VOUT
Lifecycle:
New from this manufacturer.
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