AD5532
Rev. D | Page 15 of 20
TRACK
FUNCTION (ISHA MODE)
Typically in ISHA mode of operation
TRACK
is held high and
the channel begins to acquire when it is addressed. However, if
TRACK
is low when the channel is addressed, V
IN
is switched to
the output buffer and an acquisition on the channel does not
occur until a rising edge of
TRACK
. At this stage, the
BUSY
pin
goes low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and V
IN
is free to change again without affecting this output value.
This is useful in an application where the user wants to ramp up
V
IN
until V
OUT
reaches a particular level (see Figure 20). V
IN
does not need to be acquired continuously while it is ramping
up.
TRACK
can be kept low and only when V
OUT
has reached its
desired voltage is
TRACK
brought high. At this stage, the
acquisition of V
IN
begins.
In the example shown, a desired voltage is required on the
output of the pin driver. This voltage is represented by one input
to a comparator. The microcontroller/microprocessor ramps up
the input voltage on V
IN
through a DAC.
TRACK
is kept low
while the voltage on V
IN
ramps up so that V
IN
is not continually
acquired. When the desired voltage is reached on the output of
the pin driver, the comparator output switches. The μC/μP then
knows what code is required to be input to obtain the desired
voltage at the DUT. The
TRACK
input is now brought high and
the part begins to acquire V
IN
. At this stage
BUSY
goes low until
V
IN
has been acquired. The output buffer is then switched from
V
IN
to the output of the DAC.
MODES OF OPERATION
The AD5532 can be used in four different modes of operation.
These modes are set by two mode bits, the first two bits in the
serial word.
Table 9. Modes of Operation
Mode Bit 1 Mode Bit 2 Operating Mode
0 0 ISHA mode
0 1 DAC mode
1 0 Acquire and Read Back
1 1 Read Back
1. ISHA Mode
In this mode, a channel is addressed and that channel acquires
the voltage on V
IN
. This mode requires a 10-bit write (see Figure
21a) to address the relevant channel (V
OUT
0–V
OUT
31, offset
channel or all channels). MSB is written first.
2. DAC Mode
In this standard mode, a selected DAC register is loaded serially.
This requires a 24-bit write (10 bits to address the relevant DAC
plus an extra 14 bits of DAC data). MSB is written first. The
user must allow 400 ns (min) between successive writes in DAC
mode.
3. Acquire and Readback Mode
This mode allows the user to acquire V
IN
and read back the data
in a particular DAC register. The relevant channel is addressed
(10-bit write, MSB first) and V
IN
is acquired in 16 μs (max).
Following the acquisition, after the next falling edge of
SYNC
,
the data in the relevant DAC register is clocked out onto the
D
OUT
line in a 14-bit serial format. The full acquisition time
must elapse before the DAC register data can be clocked out.
4. Readback Mode
Again, this is a Readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of
SYNC
, the data in the relevant DAC
register is clocked out onto the D
OUT
line in a 14-bit serial
format. The user must allow 400 ns (min) between the last
SCLK falling edge in the 10-bit write and the falling edge of
SYNC
in the 14-bit read back. The serial write and read words
can be seen in . Figure 21
This feature allows the user to read back the DAC register code
of any of the channels. In DAC mode, this is useful in
verification of write cycles. In ISHA mode, readback is useful if
the system has been calibrated and the user wants to know what
code in the DAC corresponds to a desired voltage on V
OUT
. If
this voltage is required again, the user can input the code
directly to the DAC register without going through the
acquisition sequence.
00939-C-019
TRACK
V
IN
DAC
ACQUISITION
CIRCUIT
V
OUT
1
BUSY
OUTPUT
STAGE
CONTROLLER
PIN
DRIVER
DEVICE
UNDER
TEST
THRESHOLD
VOLTAGE
ONLY ONE CHANNEL SHOWN FOR SIMPLICITY
AD5532
Figure 20. Typical ATE Circuit Using
TRACK
Input
