OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD5532ABC-3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD5532
Rev. D | Page 6 of 20
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Table 3.
Parameter
1,
2
Limit at T
MIN
, T
MAX
(A Version) Unit Conditions/Comments
t
1
0 ns min
CS
to WR setup time
t
2
0 ns min
CS
to WR hold time
t
3
50 ns min
CS
pulse width low
t
4
50 ns min
WR
pulse width low
t
5
20 ns min
A4–A0, CAL, OFFS_SEL to WR
setup time
t
6
7 ns min
A4–A0, CAL, OFFS_SEL to WR
hold time
1
See Figure 2 and Figure 3, the parallel interface timing diagrams.
2
PARALLEL INTERFACE TIMING DIAGRAMS
Guaranteed by design and characterization, not production tested.
00939-C-002
A4–A0, CAL,
OFFS_SEL
t
1
t
3
t
2
t
4
t
5
t
6
CS
WR
Figure 2. Parallel Write (ISHA Mode Only)
00939-C-003
200μAI
OL
200μAI
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
Figure 3. Load Circuit for D
OUT
Timing Specifications
AD5532
Rev. D | Page 7 of 20
SERIAL INTERFACE
Table 4.
Parameter
1,
2
Limit at T
MIN
, T
MAX
(A Version) Unit Conditions/Comments
f
CLKIN
3
14 MHz max SCLK frequency
t
1
28 ns min SCLK high pulse width
t
2
28 ns min SCLK low pulse width
SYNC
falling edge to SCLK falling edge setup time
t
3
15 ns min
SYNC
low time
t
4
50 ns min
t
5
10 ns min D
IN
setup time
t
6
5 ns min D
IN
hold time
SYNC
falling edge to SCLK rising edge setup time for read back
t
7
5 ns min
t
8
4
20 ns max SCLK rising edge to D
OUT
valid
t
9
4
60 ns max
SCLK falling edge to D
OUT
high impedance
10th SCLK falling edge to
SYNC
falling edge for read back
t
10
400 ns min
24th SCLK falling edge to
SYNC
falling edge for DAC mode write
t
11
400 ns min
SCLK falling edge to
SYNC
falling edge setup time for read back
t
12
5
7 ns min
00939-C-004
t
1
t
3
t
2
MSB LSB
SCLK
12345678910
SYNC
D
IN
t
4
t
5
t
6
Figure 4. 10-Bit Write (ISHA Mode and Both Readback Modes)
00939-C-005
SCLK
12345 21222324 1
D
IN
SYNC
t
1
t
3
t
2
t
4
t
5
t
6
LSBMSB
t
11
Figure 5. 24-Bit Write (DAC Mode)
00939-C-006
SCLK
10 1234567891011121314
MSB LSB
D
OUT
SYNC
t
7
t
1
t
2
t
12
t
4
t
8
t
10
t
9
Figure 6. 14-Bit Read (Both Readback Modes)
1
See Figure 4, Figure 5, and Figure 6.
2
Guaranteed by design and characterization, not production tested.
3
In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulse width is 20 ns.
4
These numbers are measured with the load circuit of Figure 3.
5
SYNC
should be taken low while SCLK is low for read back.
AD5532
Rev. D | Page 8 of 20
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C unless otherwise noted.
Table 5.
Parameter
1
Rating
V
DD
to AGND
−0.3 V to +17 V
V
SS
to AGND
+0.3 V to −17 V
AV
CC
to AGND, DAC_GND
−0.3 V to +7 V
DV
CC
to DGND
−0.3 V to +7 V
Digital Inputs to DGND
−0.3 V to DV
CC
+ 0.3 V
Digital Outputs to DGND
−0.3 V to DV
CC
+ 0.3 V
REF_IN to AGND, DAC_ GND
−0.3 V to AV
CC
+ 0.3 V
V
IN
to AGND, DAC_GND
−0.3 V to AV
CC
+ 0.3 V
V
OUT
0–31 to AGND
V
SS
− 0.3 V to V
DD
+ 0.3 V
OFFS_IN to AGND
V
SS
− 0.3 V to V
DD
+ 0.3 V
OFFS_OUT to AGND AGND - 0.3 V to AV
CC
+ 0.3 V
AGND to DGND
−0.3 V to +0.3 V
Operating Temperature Range
Industrial
−40°C to +85°C
Storage Temperature Range
−65°C to +150°C
Junction Temperature (T
J
max) 150°C
74-Lead CSPBGA Package,
θ
JA
Thermal Impedance
41°C/W
Reflow Soldering
Peak Temperature
AD5532ABC-x 220°C
AD5532ABCZ-x 260°C
Time at Peak Temperature 10 sec to 40 sec
Max Power Dissipation
(150°C − T
A
)/θ
JA
mW
2
Max Continuous Load Current at
T
J
= 70°C, per Channel Group
15 mA
3
1
Transient currents of up to 100 mA do not cause SCR latch-up.
2
This limit includes load power.
3
This maximum allowed continuous load current is spread over 8 channels
and channels are grouped as follows:
Group 1: Channels 3, 4, 5, 6, 7, 8, 9, 10
Group 2: Channels 14, 16, 18, 20. 21, 24, 25, 26
Group 3: Channels 15, 17, 19, 22, 23, 27, 28, 29
Group 4: Channels 0, 1, 2, 11, 12, 13, 30, 31
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
For higher junction temperatures derate as follows:
TJ (°C) Max Continuous Load Current per Group (mA)
70 15.5
90 9.025
100 6.925
110 5.175
125 3.425
135 2.55
150 1.5
ESD CAUTION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD5532ABC-3

Mfr. #:
Buy AD5532ABC-3
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 32 CH 14-BIT Bipolar VOUT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet