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8735BKI-01LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
8735BI-01 REVISION 1 04/02/15 1 ©2015 Integrated Device Technology, Inc.
DATA SHEET
Low Skew, 1-to-5, Differential-to-3.3V
LVPECL/ECL Fanout Buffer
8735BI-01
General Description
The 8735BI-01 is a highly versatile 1:5 Differential- to-3.3V LVPECL
clock generator. The 8735BI-01 has a fully integrated PLL and can be
configured as zero delay buffer, multiplier or divider, and has an
output frequency range of 31.25MHz to 700MHz. The reference
divider, feedback divider and output divider are each programmable,
thereby allowing for the following output-to-input frequency ratios:
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the
device to achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock is
routed around the PLL and into the internal output dividers.
Features
• Five differential 3.3V LVPECL output pairs
• Selectable differential input pairs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Static phase offset: 200ps (maximum)
• Cycle-to-cycle jitter: 50ps (maximum)
• Output skew: 55ps (maximum)
• 3.3V output operating supply
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram
PLL_SEL
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1: 8
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
0
1
CLK0
nCLK0
Pulldown
Pullup
CLK1
nCLK1
Pulldown
Pullup
CLK_SEL
Pulldown
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
2 REVISION 1 04/02/15
8735BI-01 DATA SHEET
Pin Assignments
Pin Description and Pin Characteristic Table
Table 1. Pin Descriptions
32-pin, 5mm x 5mm VFQFN Package
8735BI-01
V
CCO
nQ1
Q1
nQ2
Q2
nQ3
Q3
V
CCO
V
CC
PLL_SEL
nQ4
V
CCO
V
EE
Q4
V
CCA
SEL3
MR
CLK_SEL
nCLK1
CLK1
nCLK0
CLK0
SEL1
SEL0
V
CC
nFB_IN
FB_IN
SEL2
V
EE
nQ0
Q0
V
CCO
9
10 11 12 13 14 15 16
24
23
22
21
20
19
18
17
32
31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
32-pin, 7mm x 7mm LQFP Package
8735BI-01
MR
CLK_SEL
nCLK1
CLK1
nCLK0
CLK0
SEL1
SEL0
V
CC
nFB_IN
FB_IN
SEL2
V
EE
nQ0
Q0
V
CCO
32
31 30 29 28 27 26 25
9
10 11 12 13 14 15 16
V
CCO
nQ1
Q1
nQ2
Q2
nQ3
Q3
V
CCO
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
V
CC
PLL_SEL
nQ4
V
CCO
V
EE
Q4
V
CCA
SEL3
Number Name Type Description
1 SEL0 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
2 SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
3 CLK0 Input Pulldown Non-inverting differential clock input.
4 nCLK0 Input Pullup Inverting differential clock input.
5 CLK1 Input Pulldown Non-inverting differential clock input.
6 nCLK1 Input Pullup Inverting differential clock input.
7 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK1, nCLK1. When LOW, selects
CLK0, nCLK0. LVCMOS/LVTTL interface levels.
8 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. LVCMOS /
LVTTL interface levels.
9V
CC
Power Core supply pins.
10 nFB_IN Input Pullup Feedback input to phase detector for regenerating clocks with “Zero Delay.”
11 FB_IN Input Pulldown Feedback input to phase detector for regenerating clocks with “Zero Delay.”
12 SEL2 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
13 V
EE
Power Negative power supply pins.
14 nQ0 Output Differential output pair. LVPECL interface levels.
15 Q0 Output Differential output pair. LVPECL interface levels.
16 V
CCO
Power Output supply pins.
8735BI-01 Data Sheet
REVISION 1 04/02/15 3 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
17 V
CCO
Power Output supply pins.
18 nQ1 Output Differential output pair. LVPECL interface levels.
19 Q1 Output Differential output pair. LVPECL interface levels.
20 nQ2 Output Differential output pair. LVPECL interface levels.
21 Q2 Output Differential output pair. LVPECL interface levels.
22 nQ3 Output Differential output pair. LVPECL interface levels.
23 Q3 Output Differential output pair. LVPECL interface levels.
24 V
CCO
Power Output supply pins.
25 V
CCO
Power Output supply pins.
26 nQ4 Output Differential output pair. LVPECL interface levels.
27 Q4 Output Differential output pair. LVPECL interface levels.
28 V
EE
Power Negative power supply pins.
29 SEL3 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
30 V
CCA
Power Analog supply pin.
31 PLL_SEL Input Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
32 V
CC
Power Core supply pins.
Number Name Type Description
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

8735BKI-01LF

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Description:
IC CLK GEN LVPECL ZD 1:5 32VFQFN
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