FAN5250
12 REV. 1.1.6 3/12/03
Figure 12. Improving Current Sensing Accuracy
More accurate sensing can be achieved by using a resistor
(R1) instead of the RDSon of the FET as shown in Figure 12.
This approach causes higher losses, but yields greater
accuracy in both V
DROOP
and I
LIMIT
. R1 is a low value
(e.g. 10mΩ) resistor.
Current limit (I
LIMIT
) should be set sufficiently high as to
allow the output slew rate required by the design, since the
output capacitors will have to be charged during this slew.
The dv/dt term we used earlier in the discussion (set up by
the C
SS
) was 50mV/32µS or 1.56V/mS. In addition, since
I
LIMIT
is a peak current cut-off value, we will need to multi-
ply the result by the inductor ripple current (we'll use 30%).
Assuming C
OUT
of 1000µF, and a maximum load current of
6A the target for I
LIMIT
would be:
Gate Driver Section
The gate control logic translates the internal PWM control
signal into the MOSFET gate drive signals providing
necessary amplification, level shifting and shoot-through
protection. Also, it has functions that help optimize the IC
performance over a wide range of operating conditions.
Since MOSFET switching time can vary dramatically from
type to type and with the input voltage, the gate control
logic provides adaptive dead time by monitoring the
gate-to-source voltages of both upper and lower MOSFETs.
The lower MOSFET drive is not turned on until the
gate-to-source voltage of the upper MOSFET has decreased
to less than approximately 1 Volt. Similarly, the upper
MOSFET is not turned on until the gate-to-source voltage of
the lower MOSFET has decreased to less than approximately
1 volt. This allows a wide variety of upper and lower
MOSFETs to be used without a concern for simultaneous
conduction, or shoot-through.
There must be a low – resistance, low – inductance path
between the driver pin and the MOSFET gate for the adap-
tive dead-time circuit to work properly. Any delay along that
path will subtract from the delay generated by the adaptive
dead-time circuit and a shoot-through condition may occur.
Frequency Loop Compensation
Due to the implemented current mode control, the modulator
has a single pole response with -1 slope at frequency
determined by load
where R
O
is load resistance, C
O
is load capacitance. For this
type of modulator Type 2 compensation circuit is usually
sufficient. To reduce the number of external components and
simplify the design task, the PWM controller has an inter-
nally compensated error amplifier. Figure 13 shows a Type 2
amplifier and its response along with the responses of a cur-
rent mode modulator and of the converter. The Type 2 ampli-
fier, in addition to the pole at the origin, has a zero-pole pair
that causes a flat gain region at frequencies between the zero
and the pole.
Figure 13. Compensation
This region is also associated with phase ‘bump’ or reduced
phase shift. The amount of phase shift reduction depends on
how wide the region of flat gain is and has a maximum value
of 90°. To further simplify the converter compensation, the
modulator gain is kept independent of the input voltage
variation by providing feed-forward of VIN to the oscillator
ramp.
The zero frequency, the amplifier high frequency gain and
the modulator gain are chosen to satisfy most typical appli-
cations. The crossover frequency will appear at the point
where the modulator attenuation equals the amplifier high
LDRV
22
PGND
ISNS
21
R
SENSE
R1
Q2
I
LIMIT
I
LOAD
> C
OUT
dV
dt
-------
+
(11a)
I
LIMIT
1.3 6A 1mF 1.56V mS⁄×()+()13A≈>
(11b)
F
P0
1
2πR
O
C
O
------------------------=
(12)
R1
R2
EA Out
C1
C2
REF
V
IN
Converter
0
14
18
modulator
F
P0
F
Z
F
P
error amp
F
Z
1
2πR
2
C
1
---------------------- 6 kHz==
F
p
1
2πR
2
C
1
---------------------- 600 kHz==
(13a)
(13b)
