FAN5250
REV. 1.1.6 3/12/03 13
frequency gain. The only task that the system designer has to
complete is to specify the output filter capacitors to position
the load main pole somewhere within one decade lower than
the amplifier zero frequency. With this type of compensation
plenty of phase margin is easily achieved due to zero-pole
pair phase ‘boost’.
Conditional stability may occur only when the main load
pole is positioned too much to the left side on the frequency
axis due to excessive output filter capacitance. In this case,
the ESR zero placed within the 10kHz...50kHz range gives
some additional phase ‘boost’. Fortunately, there is an oppo-
site trend in mobile applications to keep the output capacitor
as small as possible.
Protection
The converter output is monitored and protected against
extreme overload, short circuit, over-voltage and
under-voltage conditions.
A sustained overload on the output sets the PGOOD pin low
and latches-off the whole chip. Operation can be restored by
cycling the VCC voltage or enabling (EN) pin.
Over-Current Sensing
When the circuit's current limit signal (“ILIM det” as shown
in Figure 7) goes high, a pulse-skipping circuit is activated.
HDRV will be inhibited as long as the sensed current is
higher than the ILIM value. This limits the current supplied
by the DC input. This condition continues for 8 clock cycles
after the over-current comparator was tripped for the first
time. If after these first 8 clock cycles the current exceeds the
over-current threshold again at any time within the subse-
quent 8 clock cycles, the overcurrent protection circuit is
latched and the chip is disabled. If "ILIM det" goes away
during the first 8 clock cycles, normal operation is restored
and the over-current circuit resets itself 16 clock cycles after
the over-current threshold was exceeded for the first time.
If the load step is strong enough to pull the V
CORE
+ lower
than the under-voltage threshold, the chip shuts down
immediately.
Over-Voltage Protection
Should the output voltage exceed 1.9V due to an upper
MOSFET failure, or for other reasons, the overvoltage
protection comparator will force the LDRV high. This action
actively pulls down the output voltage and, in the event of
the upper MOSFET failure, will eventually blow the battery
fuse. As soon as the output voltage drops below the
threshold, the OVP comparator is disengaged.
This OVP scheme provides a ‘soft’ crowbar function which
helps to tackle severe load transients and does not invert the
output voltage when activated — a common problem for
OVP schemes with a latch.
Over-Temperature Protection
The chip incorporates an over temperature protection circuit
that shuts the chip down when a die temperature of 150˚C
is reached. Normal operation is restored at die temperature
below 125°C with internal Power On Reset asserted,
resulting in a full soft-start cycle.
Design and Component Selection
Guidelines
As an initial step, define operating voltage range and mini-
mum and maximum load currents for the controller.
Output Inductor Selection
The minimum practical output inductor value is the one that
keeps inductor current just on the boundary of continuous
conduction at some minimum load. The industry standard
practice is to choose the minimum current somewhere from
15% to 35% of the nominal current. At light load, the con-
troller can automatically switch to hysteretic mode of opera-
tion to sustain high efficiency. The following equations help
to choose the proper value of the output filter inductor.
where I is the inductor ripple current and V
OUT
is the
maximum ripple allowed.
for this example we'll use:
Therefore,
CH1 5.0V
CH3 2.0A
CH2 100mV
M 10.0µs
Shutdown
1
2
3
VOUT
8 CLK
IL
PGOOD
I2= I
MIN
V
OUT
ESR
------------------=×
L
V
IN
V
OUT
F
SW
I×
------------------------------
V
OUT
V
IN
--------------
×=
V
IN
20V V
OUT
1V=,=
I30%= 5A 1.25A=×
F
SW
300KHz=
L 1.8µH
FAN5250
14 REV. 1.1.6 3/12/03
Output Capacitor Selection
The output capacitor serves two major functions in a switch-
ing power supply. Along with the inductor it filters the
sequence of pulses produced by the switcher, and it supplies
the load transient currents. The filtering requirements are a
function of the switching frequency and the ripple current
allowed, and are usually easy to satisfy in high frequency
converters.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
Modern microprocessors produce transient load rates in
excess of 10A/µs. High frequency ceramic capacitors placed
beneath the processor socket initially supply the transient
and reduce the slew rate seen by the bulk capacitors. The
bulk capacitor values are generally determined by the total
allowable ESR rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the processor power pins as physically possible.
Consult with the processor manufacturer for specific decou-
pling requirements. Use only specialized low-ESR electro-
lytic capacitors intended for switching-regulator applications
for the bulk capacitors. The bulk capacitor’s ESR will deter-
mine the output ripple voltage and the initial voltage drop
after a transient. In most cases, multiple electrolytic capaci-
tors of small case size perform better than a single large case
capacitor.
Power MOSFET Selection
For the example in the following discussion, we will be
selecting components for:
V
IN
from 5V to 20V
V
OUT
= 1.2V @ I
LOAD(MAX)
= 7A
The FAN5250 converter's output voltage is very low with
respect to the input voltage, therefore the Lower MOSFET
(Q2) is conducting the full load current for most of the cycle.
Therefore, Q2 should be selected to be a MOSFET with low
R
DS(ON)
to
minimize conduction losses.
In contrast, Q1 is on for a maximum of 20% (when V
IN
=
5V) of the cycle, and its conduction loss will have less of an
impact. Q1, however, sees most of the switching losses, so
Q1’s primary selection criteria should be gate charge
(Q
G(SW)
).
High-Side Losses:
Figure 14. Switching Losses and Q
G
Figure 15. Drive Equivalent Circuit
Assuming switching losses are about the same for both the
rising edge and falling edge, Q1’s switching losses, as can be
seen by Figure 14, are given by:
Where R
DS(ON)
is @T
J(MAX)
and t
S
is the switching period
(rise or fall time) and is predominantly the sum of t2, t3
(Figure 14), a function of the impedance of the driver and the
Q
G(SW)
of the MOSFET. Since most of t
S
occurs when V
GS
= V
SP
we can use a constant current assumption for the
driver to simplify the calculation of t
S
:
V
SP
t1 t2 t3
4.5V
t4 t5
Q
G(SW)
V
DS
I
D
Q
GS
Q
GD
V
TH
V
GS
C
ISS
C
RSS
C
ISS
C
ISS
= C
GS
|| C
GD
C
GD
R
D
G
R
GATE
C
GS
19
HDRV
5V
20
SW
VIN
P
UPPER
P
SW
= P
COND
+
P
SW
V
DS
I
L
×
2
---------------------
2t
S
××


F
SW
=
P
COND
V
OUT
V
IN
--------------
I
OUT
2
R
DS ON()
××=
(14a)
(14b)
(14c)
t
S
Q
GSW()
I
DRIVER
---------------------
Q
GSW()
VDD V
SP
R
DRIVER
R
GATE
+
------------------------------------------------


------------------------------------------------------
=
(15)
FAN5250
REV. 1.1.6 3/12/03 15
For the high-side MOSFET, V
DS
= VIN, which can be as
high as 20V in a typical portable application. Q2, however,
switches on or off with its parallel shottky diode conducting,
therefore V
DS
0.5V. Since P
SW
is proportional to V
DS
, Q2's
switching losses are negligible and we can select Q2 based
on R
DS(ON)
only.
Care should also be taken to include the delivery of the
MOSFET's gate power (P
GATE
) in calculating the power
dissipation required for the FAN5250:
Low-Side Losses
Conduction losses for Q2 are given by:
where R
DS(ON)
is the R
DS(ON)
of the MOSFET at the highest
operating junction temperature and is the
minimum duty cycle for the converter. Since D
MIN
is 5% for
portable computers, (1-D) 1, further simplifying the calcu-
lation.
The maximum power dissipation (P
D(MAX)
) is a function of
the maximum allowable die temperature of the low-side
MOSFET, the θ
J-A
, and the maximum allowable ambient
temperature rise:
θ
J-A
, depends primarily on the amount of PCB area that can
be devoted to heat sinking (see FSC app note AN-1029 for
SO-8 MOSFET thermal information).
Table 2. Suggested Component Values
Layout Considerations
Switching converters, even during normal operation, pro-
duce short pulses of current which could cause substantial
ringing and be a source of EMI if layout constrains are not
observed.
There are two sets of critical components in a DC-DC
converter. The switching power components process large
amounts of energy at high rate and are noise generators. The
low power components responsible for bias and feedback
functions are sensitive to noise.
A multi-layer printed circuit board is recommended.
Dedicate one solid layer for a ground plane. Dedicate
another solid layer as a power plane and break this plane into
smaller islands of common voltage levels.
Notice all the nodes that are subjected to high dV/dt voltage
swing such as SW, HDRV and LDRV, for example. All
surrounding circuitry will tend to couple the signals from
these nodes through stray capacitance. Do not oversize
copper traces connected to these nodes. Do not place traces
connected to the feedback components adjacent to these
traces.
It is not recommended to use High Density Interconnect
Systems, or micro-vias on these signals. The use of blind or
buried vias should be limited to the low current signals only.
The use of normal thermal vias is left to the discretion of the
designer.
Keep the wiring traces from the IC to the MOSFET gate and
source as short as possible and capable of handling peak
currents of 2A. Minimize the area within the gate-source
path to reduce stray inductance and eliminate parasitic
ringing at the gate.
Locate small critical components like the soft-start capacitor
and current sense resistors as close as possible to the respec-
tive pins of the IC.
The FAN5250 utilizes advanced packaging technology that
will have lead pitch of 0.6mm. High performance analog
semiconductors utilizing narrow lead spacing may require
special considerations in PWB design and manufacturing.
It is critical to maintain proper cleanliness of the area sur-
rounding these devices. It is not recommended to use any
type of rosin or acid core solder, or the use of flux in either
the manufacturing or touch up process as these may contrib-
ute to corrosion or enable electromigration and/or eddy
currents near the sensitive low current signals. When
chemicals such as these are used on or near the PWB, it is
suggested that the entire PWB be cleaned and dried com-
pletely before applying power.
Design 1 Design 2 Design 3
I
CPU(MAX)
6 A 12 A 18 A
Inductor 1.8µH
Sumida
CEP1231R8MH
1.0µH
Panasonic
ETQP6F1R0BFA
0.8µH
Panasonic
ETQP6F0R8BFA
Output Caps 4 x 220µF
Sanyo
POSCAP
2R5TPC220M
or
3 x 270µF
Panasonic
EEFUE271R
6 x 220µF
Sanyo
POSCAP
2R5TPC220M
or
5 x 270µF
Panasonic
EEFUE271R
6 x 270µF
Panasonic
EEFUE271R
High-Side
MOSFETs
FDS6612A FDS6694 FDS6694
Low-Side
MOSFETs
FDS6690S 2 X FDS6672A 2 X FDS7764A
R
SNS
for 3%
droop
3.57K 2.8K 3K
P
GATE
Q
G
VDD F
SW
××=
(16)
(17)
P
COND
1D()I
OUT
2
× R
DS ON()
×=
D
V
OUT
V
IN
--------------=
P
D MAX()
T
J MAX()
T
A MAX()
Θ
JA
-------------------------------------------------=

FAN5250QSCX

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG CONV MOBILE 1OUT 24QSOP
Lifecycle:
New from this manufacturer.
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