FAN5250
REV. 1.1.6 3/12/03
7
Circuit Description
Overview
The FAN5250 is a single output power management IC
supplies the low-voltage, high-current power to modern
processors for notebook and sub-notebook PCs. Using very
few external components, the IC controls a precision pro-
grammable synchronous buck converter driving external
N-Channel power MOSFETs. The output voltage is adjust-
able from 0.6V to 1.75V by changing the DAC code settings
(see Table 1). Alternatively, the output voltage can be set by
an analog input. This feature is important in systems where
VID code may not be established during start-up or CPU
core power saving modes. The output voltage of the core
converter can be changed on-the-fly with programmable slew
rate, which meets a key requirement of the processor.
The converter can operate in two modes: fixed frequency
PWM, and variable frequency hysteretic depending on the
load. At loads lower than the point where filter inductor
current becomes discontinuous, hysteretic mode of operation
is activated. Switchover from PWM to hysteretic operation at
light loads improves the converter's efficiency and prolongs
battery run time. As the filter inductor resumes continuous
current, the PWM mode of operation is restored. The chip
can be prevented from entering hysteretic mode by driving
the FPWM pin low.
The core converter incorporates a proprietary output voltage
droop method for optimum handling of fast load transients
found in modern processors.
Initialization and Soft Start
Assuming EN is high, FAN5250 is initialized when power
is applied on VCC. Should VCC drop below the UVLO
threshold, an internal Power-On Reset function disables
the chip.
The IC attempts to regulate the VCORE output according to
the voltage that appears on the SS pin (V
SS
). During start-up
of the converter, this voltage is initially 0, and rises linearly
to 0.5V via the current supplied to C
SS
through the 25µA
internal current source. The time it takes to reach 0.5V is:
where T
0.5
is in seconds if C
SS
is in µF.
At that point, the current source changes to 500µA, which
then sets the slew rate of voltage changes at the output in
response to changes in VID.
This dual slope approach helps to provide safe rise of
voltages and currents in the converters during initial start-up
and at the same time sets a controlled speed of the core
voltage change when the processor commands to do so.
Figure 3. Soft-Start Function
C
SS
typically is chosen based on the slew rate desired in
response to a VID change. For example, if the spec requires a
50mV step to occur in 32µS:
With this value of C
SS
, the time for the output voltage to rise
to 0.5V if found using equation 1:
T
0.5
= 6.6mS
We defined a slew rate of 50mV/32µS to choose the
capacitor, therefore it takes an additional 450µS to rise
from 0.5V to 1.2V.
Converter Operation
At nominal current the converter operates in fixed frequency
PWM mode. The output voltage is compared with a
reference voltage set by the DAC, which appears on the SS
pin. The derived error signal is amplified by an internally
compensated error amplifier and applied to the inverting
input of the PWM comparator. To provide output voltage
droop for enhanced dynamic load regulation, a signal
proportional to the output current is added to the voltage
feedback signal. This feedback scheme in conjunction with a
PWM ramp proportional to the input voltage allows for fast
and stable loop response over a wide range of input voltage
and output current variations. For the sake of efficiency and
maximum simplicity, the current sense signal is derived from
the voltage drop across the lower MOSFET during its
conduction time.
T
0.5
0.5 C
SS
×
25
-------------------------=
1V
0
EN
SS
VCORE
PGOOD
1V
0
C
SS
∆I
SS
∆V
DAC
------------------= ∆t
500µA
50mV
------------------
32µS= 0.33µF≅
(2)
T
1.2
T
0.5
T
0.5to1.2()
6.6= 0.45++7mS==
(3)
(1)
