10 DS803F3
CS4353
DIGITAL INTERFACE CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = CPGND = 0 V; all voltages with respect to ground.
INTERNAL POWER-ON RESET THRESHOLD VOLTAGES
Test conditions (unless otherwise specified): AGND = DGND = CPGND = 0 V; all voltages with respect to ground.
Figure 2. Power-on Reset Threshold Sequence
Parameters Symbol Min Typ Max Units
High-Level Input Voltage 1.2 V <VL 3.3 V
0.9 V VL 1.2 V
V
IH
V
IH
0.7xVL
0.9xVL
-
-
-
-
V
V
Low-Level Input Voltage 1.2 V <VL 3.3 V
0.9 V VL 1.2 V
V
IL
V
IL
-
-
-
-
0.3xVL
0.1xVL
V
V
Input Leakage Current I
in
--±10A
Input Capacitance - 8 - pF
Parameters Symbol Min Typ Max Units
Internal Reset Asserted at Power-On
V
on1
-1.00- V
Internal Reset Released at Power-On
V
on2
-2.36- V
Internal Reset Asserted at Power-Off
V
off
-2.22- V
VCP
V
on2
V
on1
V
off
DGND
HI
LO
No Power
reset
undefined
reset
active
DAC
Ready
reset
active
reset
(internal)
DS803F3 11
CS4353
DC ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise specified): VCP = VA = VL = 3.3 V; AGND = DGND = CPGND = 0 V; SDIN = 0;
all voltages with respect to ground.
Notes: 15. Current consumption increases with increasing sample rate and increasing MCLK frequency. Typical
values are based on Fs = 48 kHz and MCLK = 12.288 MHz. Maximum values are based on highest
sample rate and highest MCLK frequency; see Switching Specifications - Serial Audio Interface. Vari-
ance between speed modes is small.
16. Power-down is defined as RESET
pin = Low with all clock and data lines held static low. All digital inputs
have a weak pull-down (approximately 50 k) which is only present during reset. Opposing this pull-
down will slightly increase the power-down current.
17. Valid with the recommended capacitor value on VBIAS
as shown in the typical connection diagram in
Section 3.
18. Typical voltage shown for “Initialization State”; see Section 4.8. Typical voltage may be up to 1.5 V lower
during normal operation.
2.1 Digital I/O Pin Characteristics
Input and output levels and associated power supply voltage are shown in Table 1. Logic levels should not
exceed the corresponding power supply voltage.
Table 1. Digital I/O Pin Characteristics
Parameters Symbol Min Typ Max Units
Power Supplies
Power Supply Current (Note 15)
Normal Operation
Power-Down, All Supplies (Note 16)
I
VCP
I
VA
I
VL
I
PD
-
-
-
-
36
2.4
0.1
65
43
3
0.2
-
mA
mA
mA
A
Power Dissipation (All Supplies) Normal Operation, 1_2VRMS = 0
(Note 15) Power-Down (Note 16)
-
-
127
1
152
-
mW
mW
Power Supply Rejection Ratio (Note 17) (1 kHz)
(60 Hz)
PSRR -
-
60
60
-
-
dB
dB
DC Output Voltages
Pin Voltage FLYP+ to FLYP-
VFILT+ to GND (Note 18)
FLYN+ to FLYN-
GND to VFILT- (Note 18)
VA to VBIAS
-
-
-
-
-
3.3
6.6
6.6
6.6
2.1
-
-
-
-
-
V
V
V
V
V
Pin Name Power Supply I/O Driver Receiver
RESET
VL
Input - 0.9 V - 3.3 V, with Hysteresis
MCLK Input - 0.9 V - 3.3 V
LRCK Input - 0.9 V - 3.3 V
SCLK Input - 0.9 V - 3.3 V
SDIN Input - 0.9 V - 3.3 V
DEM Input - 0.9 V - 3.3 V
I²S
/LJ Input - 0.9 V - 3.3 V
1_2VRMS Input - 0.9 V - 3.3 V
12 DS803F3
CS4353
3. TYPICAL CONNECTION DIAGRAM
VL+0.9 V to +3.3 V
RESET
LRCK
MCLK
SCLK
AOUT_REF
SDIN
VFILT-
AOUTA
V
A
562
2.2 nF
R
ext
R
ext
Line Level Out
Left & Right
I²S/LJ
DEM
1_2VRMS
VFILT+
Digital Audio
Processor
Hardware
Control
Values shown are for
Fc = 130 kHz.
Capacitors must be
C0G or equivalent.
562
2.2 nF
AOUTB
VBIAS
FLYN-
FLYN+
0.1 µF
0.1 µF
2.2 µF
FLYP-
FLYP+
2.2 µF
0.1 µF
0.1 µF
+3.3 V
0.1 µF
V
C
P
Note 1:
C
P
G
N
D
D
G
N
D
A
G
ND
22 µF
2.2 µF
2.2 µF
2.2 µF
Note 1
3
1
2
23
24
22
19
21
20
10 4 16
18
176
12
11
9
13
14
15
5
7
8
+
+
+
Note 2
Note 2:
Connect RESET
to VL if internal
power-on reset is
used.
+
CS4353
Figure 3. Typical Connection Diagram

CS4353-CNZR

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio D/A Converter ICs IC 3.3V Str DAC w/2Vrms line output
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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