CS4353-CNZR Datasheet CS4353-CNZ, CS4353-CNZR | P13-P15

DS803F3 13

CS4353

4. APPLICATIONS

4.1 Line Outputs

4.1.1 Ground-centered Outputs

An on-chip charge pump creates both positive and negative high-voltage supplies, which allows the full-

scale output swing to be centered around ground. This eliminates the need for large DC-blocking capac-

itors which create audible pops at power-on, allows the CS4353 to deliver a larger full-scale output at low-

er supply voltages, and provides improved bandwidth frequency response.

4.1.2 Full-scale Output Amplitude Control

The full-scale output voltage amplitude is selected via the 1_2VRMS pin. When the pin is connected to

VL, the full-scale output voltage at the AOUTx pins is approximately 2 V

RMS

. When the pin is connected

to GND, the full-scale output voltage at the AOUTx pins is approximately 1 V

RMS

. Additional impedance

between the AOUTx pin and the load will lower the voltage delivered to the load. See the DAC Analog

Characteristics table for the complete specifications of the full-scale output voltage.

4.1.3 Pseudo-differential Outputs

The CS4353 implements a pseudo-differential output stage. The AOUT_REF input is intended to be used

as a pseudo-differential reference signal. This feature provides common mode noise rejection with single-

ended signals. Figure 4 shows a basic diagram outlining the internal implementation of the pseudo-differ-

ential output stage, including a recommended stereo pseudo-differential output topology. If pseudo-differ-

ential output functionality is not required, simply connect the AOUT_REF pin to ground next to the

CS4353. If a split-ground design is used, the AOUT_REF pin should be connected to AGND. See the Ab-

solute Maximum Ratings table for the maximum allowable voltage on the AOUT_REF pin. Applying a DC

voltage on the AOUT_REF pin will cause a DC offset on the DAC output.

Internal Left

DAC Signal

AOUTA

AOUT_REF

Left Output

GND

(pseudo-differential traces)

AOUTB

Right Output

(pseudo-differential traces)

Internal Right

DAC Signal

Psuedo-differential output improves common

mode rejection, reducing external system noise

Figure 4. Stereo Pseudo-differential Output

14 DS803F3

CS4353

4.2 Sample Rate Range/Operational Mode Detect

The CS4353 operates in one of three operational modes. The device will auto-detect the correct mode when

the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in

Table 2. Sample rates outside the specified range for each mode are not supported. In addition to a valid

LRCK frequency, a valid serial clock (SCLK) and master clock (MCLK) must also be applied to the device

for speed mode auto-detection; see Figure 9.

Table 2. CS4353 Operational Mode Auto-Detect

4.3 System Clocking

The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.

The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the

MCLK signal according to specified ratios. The specified ratios of MCLK to LRCK, along with several stan-

dard audio sample rates and the required MCLK frequency, are illustrated in Tables 3-5.

Refer to Section 4.4 for the required SCLK timing associated with the selected Digital Interface Format and

to “Switching Specifications - Serial Audio Interface” on page 9 for the maximum allowed clock frequencies.

Table 3. Single-speed Mode Standard Frequencies

Table 4. Double-speed Mode Standard Frequencies

Table 5. Quad-speed Mode Standard Frequencies

Input Sample Rate (Fs) Mode

8 kHz - 54 kHz Single-Speed Mode

84 kHz - 108 kHz Double-Speed Mode

170 kHz - 216 kHz Quad-Speed Mode

Sample Rate

(kHz)

MCLK (MHz)

256x 384x 512x 768x 1024x

32 8.1920 12.2880 16.3840 24.5760 32.7680

44.1 11.2896 16.9344 22.5792 33.8688 45.1584

48 12.2880 18.4320 24.5760 36.8640 49.1520

Sample Rate

(kHz)

MCLK (MHz)

128x 192x 256x 384x 512x

88.2 11.2896 16.9344 22.5792 33.8688 45.1584

96 12.2880 18.4320 24.5760 36.8640 49.1520

Sample Rate

(kHz)

MCLK (MHz)

128x 192x 256x

176.4 22.5792 33.8688 45.1584

192 24.5760 36.8640 49.1520

DS803F3 15

CS4353

4.4 Digital Interface Format

The device will accept audio samples in either I²S or Left-Justified digital interface formats, as illustrated in

Table 6.

The desired format is selected via the I²S

/LJ pin. For an illustration of the required relationship between the

LRCK, SCLK and SDIN, see Figures 5-6. For all formats, SDIN is valid on the rising edge of SCLK. Also,

SCLK must have at least 32 cycles per LRCK period in the Left-Justified format.

For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Chan-

nel Serial Audio Interface: A Tutorial, available at http://www.cirrus.com.

Table 6. Digital Interface Format

Figure 5. I²S, up to 24-bit Data

Figure 6. Left-justified up to 24-bit Data

4.5 Internal High-Pass Filter

The device includes an internal digital high-pass filter. This filter prevents a constant digital offset from cre-

ating a DC voltage on the analog output pins. The filter’s corner frequency is well below the audio band; see

the Combined Interpolation & On-Chip Analog Filter Response table for filter specifications.

I²S

/LJ

Description Figure

I²S, up to 24-bit Data

Left-Justified, up to 24-bit Data

LRCK

SCLK

Left Channel

Right Channel

SDIN +3 +2 +1+5 +4

MSB

-1 -2 -3 -4 -5

+3 +2 +1+5 +4

-1 -2 -3 -4

MSB

LSB

LRCK

SCLK

Left Channel

Right Channel

SDIN +3 +2 +1+5 +4

MSB

-1 -2 -3 -4 -5

+3 +2 +1+5 +4

-1 -2 -3 -4

LSB

MSB

LSB

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

CS4353-CNZR

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Audio D/A Converter ICs IC 3.3V Str DAC w/2Vrms line output

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CS4353-CNZR

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