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CS4353-CNZR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
DS803F3 19
CS4353
4.9 Recommended Power-up and Power-down Sequences
4.9.1 Power-up Sequences
4.9.1.1 External RESET Power-up Sequence
Follow the power-up sequence below if the external RESET pin is used:
1. Hold RESET
low while the power supplies are turned on.
The VA and VCP supplies should be applied prior to or simultaneously with the VL supply. If the VL
supply is applied before the VA and VCP supplies, a DC offset will occur on the analog outputs. The
offset level is bimodal: either approximately 0.7 V below the VL supply or approximately 50 mV. The
first case can only occur if the VL supply is greater than approximately 1.2 V. Either offset level is
removed when the VA and VCP supplies are applied.
2. Set the I²S
/LJ, 1_2VRMS, and DEM configuration pins to the desired state.
3. Provide the correct MCLK, LRCK, and SCLK signals locked to the appropriate frequencies as
discussed in Section 4.3.
4. After the power supplies, configuration pins, and clock signals are stable, bring RESET
high. The
device will initiate the power-up sequence seen in Figure 9. The sequence will complete and audio
will be output from AOUTx within 50 ms after RESET
is set high.
4.9.1.2 Internal Power-on Reset Power-up Sequence
Follow the power-up sequence below if the internal power-on reset is used:
1. Hold RESET
high (connected to VL) while the power supplies are turned on.
The VA and VCP supplies should be applied prior to or simultaneously with the VL supply. If the VL
supply is applied before the VA and VCP supplies, a DC offset will occur on the analog outputs. The
offset level is bimodal: either approximately 0.7 V below the VL supply or approximately 50 mV. The
first case can only occur if the VL supply is greater than approximately 1.2 V. Either offset level is
removed when the VA and VCP supplies are applied.
The power-on reset circuitry will function as described in Section 4.7.
2. Set the I²S
/LJ, 1_2VRMS, and DEM configuration pins to the desired state.
3. After the power supplies and configuration pins are stable, provide the correct MCLK, LRCK, and
SCLK signals to progress from the ‘Power-Down State’ in the power-up sequence seen in Figure 9.
The sequence will complete and audio will be output from the AOUTx pins within 50 ms after valid
clocks are applied.
4.9.2 Power-down Sequences
4.9.2.1 External RESET
Power-down Sequence
Follow the power-down sequence below if the external RESET pin is used:
1. For minimal pops, set the input digital data to zero for at least 8192 consecutive samples.
2. Bring RESET
low.
3. Remove the power supply voltages.
4.9.2.2 Internal Power-on Reset Power-down Sequence
Follow the power-down sequence below if the internal power-on reset is used:
1. For minimal pops, set the input digital data to zero for at least 8192 consecutive samples.
20 DS803F3
CS4353
2. Remove the MCLK signal without applying any glitched pulses to the MCLK pin.
3. Remove the power supply voltages.
Note: A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum
MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A tran-
sient may occur on the analog outputs if the MCLK signal duty cycle specification is violated
when the MCLK signal is removed during normal operation; see “Switching Specifications - Serial
Audio Interface” on page 9.
4.10 Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4353 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 3 shows the recommended power ar-
rangements, with VCP, VA, and VL connected to clean supplies. It is strongly recommended that a single
ground plane be used, with the DGND, CPGND, and AGND pins all connected to this common plane.
Should it be necessary to split the ground planes, the DGND and CPGND pins should be connected to the
digital ground plane and the AGND pin should be connected to the analog ground plane. In this configura-
tion, it is critical that the digital and analog ground planes be tied together with a low-impedance connection,
ideally a strip of copper on the printed circuit board, at a single point near the CS4353.
All signals, especially clocks, should be kept away from the VBIAS pin in order to avoid unwanted coupling
into the DAC.
4.10.1 Capacitor Placement
Decoupling capacitors should be placed as close to the device as possible, with the low-value ceramic
capacitor being the closest. To further minimize impedance, these capacitors should be located on the
same PCB layer as the device. If desired, all supply pins may be connected to the same supply, but a
decoupling capacitor should still be placed on each supply pin. See DC Electrical Characteristics for the
voltage present across pin pairs. This is useful for choosing appropriate capacitor voltage ratings and ori-
entation if electrolytic capacitors are used.
The CDB4353 evaluation board demonstrates the optimum layout and power supply arrangements.
DS803F3 21
CS4353
5. DIGITAL FILTER RESPONSE PLOTS
0.4 0.5 0.6 0.7 0.8 0.9 1
−120
−100
−80
−60
−40
−20
0
Frequency(normalized to Fs)
Amplitude (dB)
0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6
−120
−100
−80
−60
−40
−20
0
Frequency(normalized to Fs)
Amplitude (dB)
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
Frequency(normalized to Fs)
Amplitude (dB)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
−0.02
−0.015
−0.01
−0.005
0
0.005
0.01
0.015
0.02
Frequency(normalized to Fs)
Amplitude (dB)
0.4 0.5 0.6 0.7 0.8 0.9 1
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6
120
100
80
60
40
20
0
Frequency(normalized to Fs)
Amplitude (dB)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

CS4353-CNZR

Mfr. #:
Buy CS4353-CNZR
Manufacturer:
Cirrus Logic
Description:
Audio D/A Converter ICs IC 3.3V Str DAC w/2Vrms line output
Lifecycle:
New from this manufacturer.
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