MAX2066
50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
______________________________________________________________________________________ 15
Pin Description
PIN NAME DESCRIPTION
1, 16, 19, 22,
24–28, 30,
31, 33–36
GND Ground
2, 3, 32,
37–40
GND Ground. See the Pin-Compatibility Considerations section.
4 DATA SPI Data Digital Input
5 CLK SPI Clock Digital Input
6 CS SPI Chip-Select Digital Input
7 VDD_LOGIC
Digital Logic Supply Input. Connect to the digital logic power supply, V
DD
. Bypass to GND with a
10nF capacitor as close as possible to the pin.
8 SER/PAR
Digital Attenuator SPI or Parallel Control Selection Logic Input. Logic 0 = parallel control,
Logic 1 = serial control.
9 STATE_A Digital Attenuator Preprogrammed Attenuation State Logic Input
State A State B Digital Attenuator
Logic = 0 Logic = 0 Preprogrammed State 1
Logic = 1 Logic = 0 Preprogrammed State 2
Logic = 0 Logic = 1 Preprogrammed State 3
10 STATE_B
Logic = 1 Logic = 1 Preprogrammed State 4
11 D4 16dB Attenuator Logic Input. Logic 0 = disable, Logic 1 = enable.
12 D3 8dB Attenuator Logic Input. Logic 0 = disable, Logic 1 = enable.
13 D2 4dB Attenuator Logic Input. Logic 0 = disable, Logic 1 = enable.
14 D1 2dB Attenuator Logic Input. Logic 0 = disable, Logic 1 = enable.
15 D0 1dB Attenuator Logic Input. Logic 0 = disable, Logic 1 = enable.
17 AMP_OUT Driver Amplifier Output (50Ω). See the Typical Application Circuit for details.
18 RSET Driver Amplifier Bias Setting. See the External Bias section.
20 AMP_IN Driver Amplifier Input (50Ω). See the Typical Application Circuit for details.
21 VC C _AMP
Driver Amplifier Supply Voltage Input. Connect to the V
CC
power supply. Bypass to GND with
1000pF and 10nF capacitors as close as possible to the pin with the smaller value capacitor
closer to the part.
23 ATTEN_OUT
5-Bit Digital Attenuator Output (50Ω). Internally matched to 50Ω. Requires an external DC
blocking capacitor.
29 ATTEN_IN
5-Bit Digital Attenuator Input (50Ω). Internally matched to 50Ω. Requires an external DC blocking
capacitor.
—EP
E xp osed P ad . Inter nal l y connected to GN D . C onnect E P to GN D for p r op er RF p er for m ance and
enhanced ther m al d i ssi p ati on.
