MAX2066
50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
______________________________________________________________________________________ 19
As an example, assume that the AGC application
requires a static attenuation adjustment to trim out gain
inconsistencies within a receiver lineup. The same AGC
circuit can also be called upon to dynamically attenuate
an unwanted blocker signal that could de-sense the
receiver and lead to an ADC overdrive condition. In this
example, the MAX2066 would be preprogrammed
(through the SPI bus) with two customized attenuation
states—one to address the static gain trim adjustment,
the second to counter the unwanted blocker condition.
Toggling just the STATE_A control bit enables the user
to switch quickly between the static and dynamic atten-
uation settings with only one I/O pin.
If desired, the user can also program two additional
attenuation states by using the STATE_B control bit as
a second I/O pin. These two additional attenuation set-
tings are useful for software-defined radio applications
where multiple static gain settings may be needed to
account for different frequencies of operation, or where
multiple dynamic attenuation settings are needed to
account for different blocker levels (as defined by multi-
ple wireless standards).
External Bias
Bias currents for the driver amplifier are set and opti-
mized through external resistors. Resistors R1 and R1A
connected to RSET (pin 18) set the bias current for the
amplifier. The external biasing resistor values can be
increased for reduced current operation at the expense
of performance. See Tables 6 and 7 for details.
+5V and +3.3V Supply Voltage
The MAX2066 features an optional +3.3V supply voltage
operation with slightly reduced linearity performance.
Pin-Compatibility Considerations
The MAX2066 is a simplified version of the MAX2065
analog/digital VGA. The MAX2066 does not contain an
analog attenuator, on-chip DAC, or internal reference.
The associated input/output pins are internally connected
to ground (Table 5). Ground the unused input/output pins
to optimize isolation. (See the
Typical Application Circuit
.)
Layout Considerations
The pin configuration of the MAX2066 has been opti-
mized to facilitate a very compact physical layout of the
device and its associated discrete components.
The exposed paddle (EP) of the MAX2066’s 40-pin thin
QFN-EP package provides a low thermal-resistance
path to the die. It is important that the PCB on which the
MAX2066 is mounted be designed to conduct heat
from the EP. In addition, provide the EP with a low-
inductance path to electrical ground. The EP must be
soldered to a ground plane on the PCB, either directly
or through an array of plated via holes.
Table 4. Preprogrammed Attenuation
State Settings
