MAX2066
50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
16 ______________________________________________________________________________________
Detailed Description
The MAX2066 high-linearity digital variable-gain amplifi-
er is a general-purpose, high-performance amplifier
designed to interface with 50Ω systems operating in the
50MHz to 1000MHz frequency range.
The MAX2066 integrates a digital attenuator to provide
31dB of gain control, as well as a driver amplifier opti-
mized to provide high gain, high IP3, low noise figure,
and low power consumption. For applications that do
not require high linearity, the bias current of the amplifi-
er can be adjusted by an external resistor to further
reduce power consumption.
The attenuator is controlled as a slave peripheral using
either the SPI-compatible interface or a parallel bus
with 31dB total adjustment range in 1dB steps. An
added feature allows “rapid-fire” gain selection
between each of the four unique steps (prepro-
grammed by the user through the SPI-compatible inter-
face). The 2-pin control allows the user to quickly
access any one of four customized attenuation states
without reprogramming the SPI bus. Because each
stage has its own external RF input and RF output, this
component can be configured to either optimize NF
(amplifier configured first), or OIP3 (amplifier last). The
device’s performance features include 22dB stand-
alone amplifier gain (amplifier only), 5.2dB NF at maxi-
mum gain (includes attenuator insertion loss), and a
high OIP3 level of +42.4dBm. Each of these features
makes the MAX2066 an ideal VGA for numerous receiv-
er and transmitter applications.
In addition, the MAX2066 operates from a single +5V
supply, or a single +3.3V supply with slightly reduced
performance, and has adjustable bias to trade current
consumption for linearity performance.
5-Bit Digital Attenuator Control
The MAX2066 integrates a 5-bit digital attenuator to
achieve a high level of dynamic range. The digital
attenuator has a 31dB control range, a 1dB step size,
and is programmed either through a dedicated 5-bit
parallel bus or through the 3-wire SPI. See the
Applications Information
section and Table 1 for attenu-
ator programming details. The attenuator can be used
for both static and dynamic power control.
Driver Amplifier
The MAX2066 includes a high-performance driver with
a fixed gain of 22dB. The driver amplifier circuit is opti-
mized for high linearity for the 50MHz to 1000MHz fre-
quency range.
Applications Information
SPI Interface and Attenuator Settings
The attenuator can be programmed through the 3-wire
SPI/MICROWIRE™-compatible serial interface using
5-bit words. Twenty-eight bits of data are shifted in MSB
first and framed by CS. When CS is low, the clock is
active and data is shifted on the rising edge of the
clock. When CS transitions high, the data is latched
and the attenuator setting changes (Figure 1). See
Table 2 for details on the SPI data format.
Table 1. Control Logic
SER/PAR ATTENUATOR
0 Parallel controlled
1 SPI controlled
MICROWIRE is a trademark of National Semiconductor Corp.
MAX2066
50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
______________________________________________________________________________________ 17
DATA
CLOCK
CS
t
EWS
t
EW
t
ES
t
CW
t
CS
DN
MSB LSB
D(N - 1) D1 D0
t
CH
Figure 1. SPI Timing Diagram
Table 2. SPI Data Format
FUNCTION BIT DESCRIPTION
D27 (MSB) 16dB step (MSB of the 5-bit word used to program the digital attenuator state 4)
D26 8dB step
D25 4dB step
D24 2dB step
Digital Attenuator State 4
D23 1dB step (LSB)
D22
D21
D20
D19
Digital Attenuator State 3
D18
5-bit word used to program the digital attenuator state 3 (see the description for digital
attenuator state 4)
D17
D16
D15
D14
Digital Attenuator State 2
D13
5-bit word used to program the digital attenuator state 2 (see the description for digital
attenuator state 4)
D12
D11
D10
D9
Digital Attenuator State 1
D8
5-bit word used to program the digital attenuator state 1 (see the description for digital
attenuator state 4)
MAX2066
50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
18 ______________________________________________________________________________________
Table 2. SPI Data Format (continued)
FUNCTION BIT DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
Reserved
D0 (LSB)
Bits D[7:0] are reserved. Set to logic 0.
Digital Attenuator Settings
Using the Parallel Control Bus
To capitalize on its fast 25ns switching capability, the
MAX2066 offers a supplemental 5-bit parallel control
interface. The digital logic attenuator-control pins
(D0–D4) enable the attenuator stages (Table 3).
Direct access to this 5-bit bus enables the user to avoid
any programming delays associated with the SPI
interface. One of the limitations of any SPI bus is the
speed at which commands can be clocked into each
peripheral device. By offering direct access to the 5-bit
parallel interface, the user can quickly shift between
digital attenuator states as needed for critical “fast-
attack” automatic gain-control (AGC) applications.
“Rapid-Fire” Preprogrammed
Attenuation States
The MAX2066 has an added feature that provides
“rapid-fire” gain selection between four prepro-
grammed attenuation steps. As with the supplemental
5-bit bus mentioned above, this “rapid-fire” gain selec-
tion allows the user to quickly access any one of four
customized digital attenuation states without incurring
the delays associated with reprogramming the device
through the SPI bus.
The switching speed is comparable to that achieved
using the supplemental 5-bit parallel bus. However, by
employing this specific feature, the digital attenuator
I/O is further reduced by a factor of either 5 or 2.5 (5
control bits vs. 1 or 2, respectively) depending on the
number of states desired.
The user can employ the STATE_A and STATE_B logic-
input pins to apply each step as required (Table 4).
Toggling just the STATE_A pin (one control bit) yields
two preprogrammed attenuation states; toggling both
the STATE_A and STATE_B pins together (two control
bits) yields four preprogrammed attenuation states.
Table 3. Digital Attenuator Settings (Parallel Control)
INPUT LOGIC = 0 (OR GROUND) LOGIC = 1
D0 Disable 1dB attenuator, or when SPI is default programmer Enable 1dB attenuator
D1 Disable 2dB attenuator, or when SPI is default programmer Enable 2dB attenuator
D2 Disable 4dB attenuator, or when SPI is default programmer Enable 4dB attenuator
D3 Disable 8dB attenuator, or when SPI is default programmer Enable 8dB attenuator
D4 Disable 16dB attenuator, or when SPI is default programmer Enable 16dB attenuator

MAX2066EVKIT

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Maxim Integrated
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KIT EVALUATION FOR MAX2066
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