MAX1249BEEE+ Datasheet MAX1249BEEE+, MAX1249AEEE+, MAX1249AEPE+ | P13-P15

MAX1248/MAX1249

+2.7V to +5.25V, Low-Power, 4-Channel,

Serial 10-Bit ADCs in QSOP-16

______________________________________________________________________________________ 13

Data Framing

The falling edge of CS does not start a conversion. The

first logic high clocked into DIN is interpreted as a start

bit and defines the first bit of the control byte. A conver-

sion starts on the falling edge of SCLK, after the eighth

bit of the control byte (the PD0 bit) is clocked into DIN.

The start bit is defined as:

The first high bit clocked into DIN with CS low any

time the converter is idle; e.g., after V

is applied.

The first high bit clocked into DIN after bit 3 of a con-

version in progress is clocked onto the DOUT pin.

If CS

is toggled before the current conversion is com-

plete, the next high bit clocked into DIN is recognized as

a start bit; the current conversion is terminated, and a

new one is started.

The fastest the MAX1248/MAX1249 can run with CS

held low between conversions is 15 clocks per conver-

sion. Figure 10a shows the serial-interface timing nec-

essary to perform a conversion every 15 SCLK cycles

in external clock mode. If CS is tied low and SCLK is

continuous, guarantee a start bit by first clocking in 16

zeros.

Most microcontrollers require that conversions occur in

multiples of 8 SCLK clocks; 16 clocks per conversion is

typically the fastest that a microcontroller can drive the

MAX1248/MAX1249. Figure 10b shows the serial-inter-

face timing necessary to perform a conversion every 16

SCLK cycles in external clock mode.

__________ Applications Information

Power-On Reset

When power is first applied, and if SHDN is not pulled

low, internal power-on reset circuitry activates the

MAX1248/MAX1249 in internal clock mode, ready to

convert with SSTRB = high. After the power supplies

have stabilized, the internal reset time is 10µs, and no

conversions should be performed during this phase.

SSTRB is high on power-up and, if CS is low, the first

logical 1 on DIN is interpreted as a start bit. Until a con-

version takes place, DOUT shifts out zeros (also see

Table 4).

Reference-Buffer Compensation

In addition to its shutdown function, SHDN selects inter-

nal or external compensation. The compensation

affects both power-up time and maximum conversion

speed. The 100kHz minimum clock rate is limited by

droop on the sample-and-hold, and is independent of

the compensation used.

PD0 CLOCK IN

SSTRB

CSH

CONV

SCK

SSTRB

SCLK

DOUT

CSS

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

• • •

Figure 9. Internal Clock Mode SSTRB Detailed Timing

MAX1248/MAX1249

+2.7V to +5.25V, Low-Power, 4-Channel,

Serial 10-Bit ADCs in QSOP-16

14 ______________________________________________________________________________________

Float SHDN to select external compensation. The

Typical Operating Circuit

uses a 4.7µF capacitor at

VREF. A value of 4.7µF or greater ensures reference-

buffer stability and allows converter operation at the

2MHz full clock speed. External compensation increas-

es power-up time (see

Choosing Power-Down Mode

and Table 4).

Pull SHDN high to select internal compensation.

Internal compensation requires no external capacitor at

VREF and allows for the shortest power-up times. The

maximum clock rate is 2MHz in internal clock mode

and 400kHz in external clock mode.

Choosing Power-Down Mode

You can save power by placing the converter in a low-

current shutdown state between conversions. Select full

power-down or fast power-down mode via bits 1 and 0

of the DIN control byte with SHDN high or floating

(Tables 1 and 5). In both software power-down modes,

the serial interface remains operational, but the ADC

does not convert. Pull SHDN low at any time to shut

down the converter completely. SHDN overrides bits 1

and 0 of the control byte.

Full power-down mode turns off all chip functions that

draw quiescent current, reducing supply current typically

to 2µA. Fast power-down mode turns off all circuitry

except the bandgap reference. With fast power-down

mode, the supply current is 30µA. Power-up time can be

shortened to 5µs in internal compensation mode.

Table 4 shows how the choice of reference-buffer com-

pensation and power-down mode affects both power-up

delay and maximum sample rate. In external compensa-

tion mode, power-up time is 20ms with a 4.7µF compen-

sation capacitor when the capacitor is initially fully

discharged. From fast power-down, start-up time can be

eliminated by using low-leakage capacitors that do not

discharge more than 1/2LSB while shut down. In power-

down, leakage currents at VREF cause droop on the ref-

erence bypass capacitor. Figures 11a and 11b show

the various power-down sequences in both external and

internal clock modes.

SCLK

DIN

DOUT

S CONTROL BYTE 0

CONTROL BYTE 1S

CONVERSION RESULT 0

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

CONVERSION RESULT 1

SSTRB

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

CONTROL BYTE 2S

8 1 8 1

SCLK

DIN

DOUT

S CONTROL BYTE 0

CONTROL BYTE 1S

CONVERSION RESULT 0

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 B9 B8 B7 B6

CONVERSION RESULT 1

• • •

Figure 10a. External Clock Mode, 15 Clocks/Conversion Timing

Figure 10b. External Clock Mode, 16 Clocks/Conversion Timing

POWERED UP

HARDWARE

POWER-

DOWN

POWERED UP

10+2 DATA BITS

INVALID

DATA

VALID

DATA

EXTERNAL

S X

X X X X

1 1 S 0 0

X XXXX X X X X X

S 1 1

SOFTWARE

POWER-DOWN

MODE

DOUT

DIN

CLOCK

MODE

SHDN

SETS EXTERNAL

CLOCK MODE

SETS EXTERNAL

CLOCK MODE

SETS SOFTWARE

POWER-DOWN

POWERED UP

DATA VALID

INTERNAL

S X

X X X X

1 0 S 0 0

X XXXX

MODE

DOUT

DIN

CLOCK

MODE

SETS INTERNAL

CLOCK MODE

SETS

POWER-DOWN

CONVERSION

SSTRB

Figure 11a. Timing Diagram Power-Down Modes, External Clock

Figure 11b. Timing Diagram Power-Down Modes, Internal Clock

MAX1248/MAX1249

+2.7V to +5.25V, Low-Power, 4-Channel,

Serial 10-Bit ADCs in QSOP-16

______________________________________________________________________________________ 15

REFERENCE

BUFFER

REFERENCE-BUFFER

COMPENSATION

MODE

VREF

CAPACITOR

(µF)

POWER-DOWN

MODE

POWER-UP

DELAY

(µs)

MAXIMUM

SAMPLING RATE

(ksps)

Disabled — — Full 2 133

Enabled Internal — Fast 5 26

Enabled Internal — Full 300 26

Enabled External 4.7 Fast See Figure 13c 133

Enabled External 4.7 Full See Figure 13c 133

Disabled — — Fast 2 133

Table 4. Typical Power-Up Delay Times

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

MAX1249BEEE+

Mfr. #:

Buy MAX1249BEEE+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 10-Bit 4Ch 133ksps 5.25V Precision ADC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX1249BEEE+

MAX1249BEEE+

Products related to this Datasheet