MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
16 ______________________________________________________________________________________
Software Power-Down
Software power-down is activated using bits PD1 and PD0
of the control byte. As shown in Table 5, PD1 and PD0
also specify the clock mode. When software shutdown is
asserted, the ADC operates in the last specified clock
mode until the conversion is complete. Then the ADC
powers down into a low quiescent-current state. In internal
clock mode, the interface remains active, and conversion
results may be clocked out after the MAX1248/MAX1249
enter a software power-down.
The first logical 1 on DIN is interpreted as a start bit
and powers up the MAX1248/MAX1249. Following the
start bit, the data input word or control byte also deter-
mines clock mode and power-down states. For exam-
ple, if the DIN word contains PD1 = 1, then the chip
remains powered up. If PD0 = PD1 = 0, a power-down
resumes after one conversion.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down (Table 6). Unlike software power-down
mode, the conversion is not completed; it stops coinci-
dentally with SHDN being brought low. SHDN also con-
trols the clock frequency in internal clock mode. Letting
SHDN float sets the internal clock frequency to 1.8MHz.
When returning to normal operation with SHDN floating,
there is a t
RC
delay of approximately 2MΩ x C
L
, where
C
L
is the capacitive loading on the SHDN pin. Pulling
SHDN high sets the internal clock frequency to 225kHz.
This feature eases the settling-time requirement for the
reference voltage. With an external reference, the
MAX1248/MAX1249 can be considered fully powered
up within 2µs of actively pulling SHDN high.
Power-Down Sequencing
The MAX1248/MAX1249 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 12, 13a, and 13b show
the average supply current as a function of the sampling
rate. The following discussion illustrates the various
power-down sequences.
Lowest Power at up to 500
Conversions/Channel/Second
The following examples illustrate two different power-
down sequences. Other combinations of clock rates,
compensation modes, and power-down modes may
give lowest power consumption in other applications.
Figure 13a depicts the MAX1248 power consumption
for one or eight channel conversions, utilizing full
power-down mode and internal-reference compensa-
tion. A 0.01µF bypass capacitor at REFADJ forms an
RC filter with the internal 20kΩ reference resistor with a
0.2ms time constant. To achieve full 10-bit accuracy, 8
time constants or 1.6ms are required after power-up.
Waiting 1.6ms in FASTPD mode instead of in full power-
up can reduce the power consumption by a factor of 10
or more. This is achieved by using the sequence shown
in Figure 14.
Table 5. Software Power-Down and
Clock Mode
Table 6. Hardware Power-Down and
Internal Clock Frequency
SSHHDDNN
STATE
DEVICE
MODE
REFERENCE-
BUFFER
COMPENSATION
INTERNAL
CLOCK
FREQUENCY
1 Enabled Internal
225kHz
Floating Enabled External
1.8MHz
0
Power-
Down
N/A N/A
