AD9862BSTZ Datasheet AD9860BSTZ, AD9862BSTZ, AD9862BSTZRL | P13-P15

REV. 0

AD9860/AD9862

–13–

BIT 7: SDIO BiDir (Bidirectional)

Default setting is low, which indicates SPI serial port uses dedi-

cated input and output lines (i.e., 4-wire interface), SDIO and

SDO Pins, respectively. Setting this bit high configures the

serial port to use the SDIO Pin as a bidirectional data pin.

BIT 6: LSB First

Default setting is low, which indicates MSB first SPI Port Access

Mode. Setting this bit high configures the SPI port access to

LSB first mode.

BIT 5: Soft Reset

Writing a high to this register resets all the registers to their

default values and forces the DLL to relock to the input clock.

The Soft Reset Bit is a one shot register and is cleared immediately

after the register write is completed.

BIT 7: V

REF

, diff (Power-Down)

Setting this bit high will power down the ADC’s differential

references (i.e., REFT and REFB).

BIT 6: V

REF

(Power-Down)

Setting this register bit high will power down the ADC reference

circuit (i.e., V

REF

BIT 5: Rx Digital (Power-Down)

Setting this bit high will power down the digital section of the

receive path of the chip. Typically, any unused digital blocks are

automatically powered down.

BIT 4/3: Rx Channel B/Rx Channel A (Power-Down)

Either ADC or both ADCs can be powered down by setting the

appropriate register bit high. The entire Rx channel is powered

down, including the differential references, input buffer, and the

internal digital block. The bandgap reference remains active for

quick recovery.

BIT 2/1: Buffer B/Buffer A (Power-Down)

Setting either of these bits high will power down the input buffer

circuits for the respective channel. The input buffer should be

powered down when bypassed. By default, these bits are low and

the input buffers are enabled.

BIT 0: All Rx (Power-Down)

Setting this bit high powers down all circuits related to the

receive path.

BIT 7: Bypass Buffer A/Bypass Buffer B

Setting either of these bits high will bypass the respective input buf-

fer circuit. When the buffer is bypassed, the input signal is routed

directly to the switched capacitor SHA input of the RxPGA. When

operating with buffer bypassed, it should be powered down.

BIT 0–4: RxPGA A/RxPGA B

These 5-bit straight binary registers (Bit 0 is the LSB, Bit 4 is the

MSB) provide control for the programmable gain amplifiers in

the dual receive paths. A 0 dB to 20 dB gain range is accom-

plished through a switched capacitor network with fast settling

of a few clock cycles. The step size is approximately 1 dB. The

setting for these registers is hex14.

BIT 2: HS (High Speed) Duty Cycle

Setting this bit high optimizes duty cycle of the internal ADC

sampling clock. It is recommended that this bit be set high in

high speed applications when clock duty cycle affects noise and

distortion performance the most. This bit should be set high in

conjunction with Clk Dut Enable register bit.

BIT 1: Shared Ref

Setting this bit high forces the dual receive ADCs into a mode

to share their differential references to provide superior gain

matching. When this option is enabled, the REFT of Channel A

and Channel B should be connected together off-chip and the

REFB of both channels should be connected.

BIT 0: Clk Duty

Setting this bit high enables an on-chip duty cycle stabilizer (DCS)

circuit to generate the internal clock for the Rx block. This option

is useful for adjusting for high speed input clocks with skewed

duty cycle. The DCS Mode can be used with ADC sampling

frequencies over 40 MHz.

BIT 4: Three-state

Setting this bit high will force both Rx data output buses, including

the RxSYNC Pin, into a three-state mode.

BIT 3: Rx Retime

The Rx path can use either of the clock outputs, CLKOUT1 or

CLKOUT2, to latch the Rx output data. Since CLKOUT1 and

CLKOUT2 have slight phase offsets, this provides some timing

flexibility with the interface. By default, this bit is low and the

Rx output latches use CLKOUT1. Setting this bit will force the

Rx output latches to use CLKOUT2.

BIT 2: Twos Complement

Default data format for the Rx data is straight binary. Setting this

bit high will generate two’s complement data.

BIT 1: Inv RxSync

When the receive data is multiplexed onto one data port (i.e., Mux

Mode Enabled), the RxSYNC Pin can be used to decode which

channel generated the current output data at the active port.

Default condition is that RxSYNC is high when Channel A is at

the output and is low when Channel B is at the output. Setting

this bit high reverses this synchronization.

BIT 0: Mux Out

Setting this bit high enables the Rx Mux Mode. Default setting

is low, which is Dual Port Mode, (i.e., non Rx Mux Mode). When in

Rx Mux Mode, both Rx channels share the same output data bus,

pins D0A to D9A (for AD9860) or D0A to D11A (for AD9862).

The other Rx output bus (pins D0B to D9B or D0B to D11B)

outputs a low logic.

BIT 3: 2 Channel

Setting this bit low disables the Rx B output data port (pins D0B

to D9B or D11B), forcing the output pins to zero. By default, the

bit is high and both data paths are active.

BIT 2: Keep –ve

This bit selects whether the receive Hilbert filter will filter positive

or negative frequencies, assuming the filter is enabled. By default

this bit is low, which passes positive frequencies. Setting this bit

high will configure the filter to pass negative frequencies.

BIT 1: Hilbert

This bit enables or disables the Hilbert filter in the receive path.

By default, this bit is low, which disables the receive Hilbert filter.

Setting this bit high enables the receive Hilbert filter.

BIT 0: Decimate

This register enables or disables the decimation filters. By default,

the register setting is low and the decimation filter is disabled.

REV. 0–14–

AD9860/AD9862

Setting this bit high enables the decimation filters and decimates

the receive data by two.

BIT 5: Alt Timing Mode

The timing section in the data sheet describes two timing modes,

the “Normal Operation” and the “Alternate Operation” modes.

At power up, the default configuration is established from the

logic level of the Mode/TxBlank pin. If Mode/TxBlank is logic

low, the Normal Operation mode is the default; if the Mode/

TxBlank pin is held at a logic high, the Alternative Operation

mode is configured at power-up (the DLL is forced to multiply

by 4 at power-up by default in this mode). After power up, the

operation mode can be configured so that the Mode/TxBlank pin

can be used for other functions. To allow this, set this bit high.

BIT 4: TxOff Enable

By default, the Mode/TxBlank pin is not used for any transmit

synchronization. The Mode/TxBlank pin input can be used to

serve two functions, blanking the DAC outputs and slaving the

TxPGA gain control. When this bit is set high, a logic high on the

Mode/TxBlank pin forces the Tx digital block to stop clocking. In

this mode, the Tx outputs will be static, holding their last update

values. To slave the TxPGA gain control to the Mode/TxBlank

pin input, register Slave Enable (Register 17, Bit 1) needs to also

be programmed. See that register for more information.

BIT 3: Tx Digital (Power-Down)

By default this bit is low, enabling the transmit path digital to

operate as programmed through other registers. By setting this

bit high, the digital blocks are not clocked to reduce power con-

sumption. When enabled, the Tx outputs will be static, holding

their last update values.

BIT 0-2: Tx Analog (Power-Down)

Three options are available to reduce analog power consumption

for the Tx channels. The first two options disable the analog output

from Tx channel A or B independently, and the third option

disables the output of both channels and reduces the power

consumption of some of the additional analog support circuitry

for maximum power savings. With all three options, the DAC bias

current is not powered down so recovery times are fast (typically

a few clock cycles). The list below explains the different modes

and settings used to configure them.

Tx Analog

Power-Down

Power-Down Option Bits Setting [2:0]

Power-Down Tx B Channel Analog Output [1 0 0]

Power-Down Tx A Channel Analog Output [0 1 0]

Power-Down Tx A and Tx B Analog Outputs [1 1 1]

DAC A/DAC B Offset

These 10-bit, twos complement registers control a dc current

offset that is combined with the Tx A or Tx B output signal. An

offset current of up to ±12% I

OUTFS

(2.4 mA for a 20 mA full-

scale output) can be applied to either differential pin on each

channel. The offset current can be used to compensate for offsets

that are present in an external mixer stage, reducing LO leakage

at its output. Default setting is hex00, no offset current. The

offset current magnitude is set using the lower nine bits. Setting

the MSB high will add the offset current to the selected differen-

tial pin, while an MSB low setting will subtract the offset value.

DAC A/DAC B Offset Direction

This bit determines to which of the differential output pins for

the selected channel the offset current will be applied. Setting this

bit low will apply the offset to the negative differential pin. Setting

this bit high will apply the offset to the positive differential pin.

BIT 6, 7: DAC A/DAC B Coarse Gain Control

These register bits will scale the full-scale output current (I

OUTFS

)

of either Tx channel independently. I

OUT

of the Tx channels is a

function of the R

SET

resistor, the TxPGA setting, and the Coarse

Gain Control setting.

MSB, LSB Tx Channel Current Scaling

10 or 11 Does not scale output current

01 Scales output current by 1/2

00 Scales output current by 1/11

BIT 5–0: DAC A/DAC B Fine Gain

The DAC output curve can be adjusted fractionally through the

Gain Trim Control. Gain trim of up to ±4% can be achieved on

each channel individually. The Gain Trim register bits are a twos

complement attention control word.

MSB, LSB

100000 Maximum positive gain adjustment

111111 Minimum positive gain adjustment

000000 No adjustment (default)

000001 Minimum negative gain adjustment

011111 Maximum negative gain adjustment

BIT 0–7: TxPGA Gain

This 8 bit, straight binary (Bit 0 is the LSB, Bit 7 is the MSB) reg-

ister controls for the Tx programmable gain amplifier (TxPGA).

The TxPGA provides a 20 dB continuous gain range with 0.1 dB

steps (linear in dB) simultaneously to both Tx channels. By

default, this register setting is hex00.

MSB, LSB

000000 Minimum gain scaling –20 dB

111111 Maximum gain scaling 0 dB

BIT 1: Slave Enable

The TxPGA Gain is controlled through register TxPGA Gain

setting and by default is updated immediately after the register

write. If this bit is set, the TxPGA Gain update is synchronized

with the rising edge of a signal applied to the Mode/TxBlank

pin. Setting TxOff enable in Register 8 is also required.

BIT 0: TxPGA Fast (Update Mode)

The TxPGA Fast bit controls the update speed of the TxPGA.

When Fast Update mode is enabled, the TxPGA provides fast gain

settling within a few clock cycles. Default setting for this bit

is low, which indicates Normal Update mode. Fast mode is

enabled when this bit is set high.

BIT 6: Tx Retime

The Tx path can use either of the clock outputs, CLKOUT1 or

CLKOUT2, to latch the Tx input data. Since CLKOUT1 and

CLKOUT2 have slight phase offsets, this provides some timing

flexibility with the interface. By default, this bit is high and the

Tx input latches use CLKOUT1. Setting this bit low will force

the Tx latches to use CLKOUT2.

REV. 0

AD9860/AD9862

–15–

BIT 5: Q/I Order

This register indicates the order of received complex transmit

data. By default this bit is low, representing I data preceding

Q data. Alternatively, if this bit is set high, the data format is

defined as Q data preceding I data.

BIT 4: Inv TxSync

This register identifies how the first and second data sets are

identified in a complex data set using the TxSYNC bit. By default

this bit is low, and TxSYNC low indicates the first data set is at

the Tx port; TxSYNC high indicates the second data set is at the

Tx port. Setting this bit high inverts the TxSYNC bit. TxSYNC

high indicates the first of the data set, and TxSYNC low indicates

the second of the data set.

BIT 3: Twos Complement

The default data format for Tx data is straight binary. Set this bit

high when providing twos complement Tx data.

BIT 2: Inverse Sample

By default, the transmit data is sampled on the rising edge of the

CLKOUT. Setting this bit high will change this, and the transmit

data will be sampled on the falling edge.

BIT 1: 2 Edges

If the CLKOUT rate is running at half the interleaved data rate,

both edges of the CLKOUT must latch transmit data. Setting

this bit high allows this clocking configuration.

BIT 0: Interleaved

By default, the AD9860/AD9862 powers up in single DAC

operation. If dual transmit data is to be used, the interleaved data

option needs to be enabled by setting this bit high.

BIT 4: 2 Data Paths

Setting this bit high enables both transmit digital paths. By default,

this bit is low and the transmit path utilizes only a single channel.

BIT 3: Keep –ve

This bit configures the Tx Hilbert filter for either positive or nega-

tive frequencies pass band, assuming it is enabled. By default

this bit is low, which selects the positive frequencies. Setting this

bit high will setup the Hilbert filter to pass negative frequencies.

BIT 2: Hilbert

This bit enables or disables the Hilbert filter in the transmit path.

By default, this bit is low, which disables the transmit Hilbert

filter. Setting this bit high enables the transmit Hilbert filter.

BIT 1,0: Interpolation Control

These register bits control the interpolation rate of the transmit

path. Default settings are both bits low, indicating that both inter-

polation filters are bypassed. The MSB and LSB are address D19,

Bits 1 and 0, respectively. Setting binary 01 provides an interpo-

lation rate of 2; binary 10 provides an interpolation rate of 4.

BIT 5: Negative Fine Tune

When this bit is low (default), the Numerically Controlled Oscil-

lator (NCO) provides positive shifts in frequency, assuming fine

modulation is enabled. Setting this bit high will use a negative

frequency shift in the Fine Complex Modulator.

BIT 4: Fine Mode

By default, the NCO and fine modulation stage are bypassed. Setting

this bit high will enable the use of the digital complex modulator,

enabling tuning with the NCO.

BIT 3: Real Mix Mode

This bit determines if the coarse modulation (controlled by register

Coarse Modulation, will perform a separate real mix on each

channel or a complex mix using the dual channel data. By default,

this bit is set low and a complex mix will be performed. Setting

this bit high will enable the Real Mix mode. Note, the Fine

Modulator Block only performs complex mixing.

BIT 2: Negative Coarse Tune

When this bit is low (default), the coarse modulator provides

positive shifts in frequency. Setting this bit high will shift the coarse

modulator processed data negative in frequency.

BIT 1,0: Coarse Modulation

These bits control what coarse modulation processing will be

performed on the transmit data. A setting of binary 00 (default)

will bypass the modulation block, a setting of binary 01 will shift

the transmit data by f

DAC

/4, and a setting of binary 10 will shift

the transmit data by f

DAC

/8.

FTW [23:0]

These three registers set the 24-bit frequency tuning word (FTW)

for the NCO in the fine modulator stage of the Tx path. The

NCO full-scale tuning word is straight binary and produces

a frequency equivalent to f

DAC

/4 with a resolution of f

DAC

BIT 6: Input Clock Control

This bit defines what type of clock will be driving the AD9860/

AD9862. The default state is low, which allows either crystal con-

nected to OSC1 and OSC2 or single-ended reference clock driving

OSC1 to drive the internal timing circuits. If a crystal will not be

used, the internal oscillator should be disabled after power-up

by setting this bit high.

BIT 5: ADC Div2

By default, the ADC is driven directly by the input clock in Normal

Timing Operation mode or the DLL output in the Alternative

Timing Operation mode. Setting this bit high will clock the ADC

at one half the previous clock rate. This is described further in

the timing section.

BIT 4,3: DLL Multiplier

These bits control the DLL multiplication factor. A setting of

binary 00 will bypass the DLL, a setting of binary 01 will multiply

the input clock by 2, and a setting of binary 10 will multiply the

input clock by 4. Default mode is defined by Mode/TxBlank

logic level at power-up or RESET, which configures either Normal

Operation Timing mode or Alternative Timing mode. In Alter-

native Timing mode, the DLL will lock to 4 multiplication

factor (the DLL FAST register remains low by default). If the

Mode/TxBlank pin is low, by default the DLL will be bypassed

and a 1 clock is used internally.

BIT 2: DLL Power-Down

Setting this register bit high forces the CLK IN multiplier to a

power-down state. This mode can be used to conserve power or

to bypass the internal DLL. To operate the AD9860/AD9862

when the DLL is bypassed, an external clock equal to the fastest

on-chip clock is supplied to the OSC pin(s).

BIT 0: DLL FAST

The DLL can be used to generate output frequencies between

32 MHz to 128 MHz. Because of the large range of locking fre-

quencies allowed, the DLL is separated into two output frequency

ranges, a “slow” range between 32 MHz to 64 MHz and a “fast”

range starting at frequencies above 64 MHz to 128 MHz. By

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

AD9862BSTZ

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Manufacturer:

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Analog Front End - AFE Mixed Signal Front-End Processor

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AD9862BSTZ

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