REV. 0
AD9860/AD9862
–7–
Pin No. Mnemonic Function
Clock Pins
10 DLL_Lock DLL Lock Indicator Pin
11, 16 AGND DLL Analog Ground Pins
12 NC No Connect
13 AVDD DLL Analog Supply Pin
14 OSC1 Single Ended Input Clock
(or Crystal Oscillator Input)
15 OSC2 Crystal Oscillator Input
17 CLKSEL Controls CLKOUT1 Rate
64 CLKOUT2 Clock Output Generated from Input
Clock (DLL Multiplier Setting
and CLKOUT2 Divide Factor)
65 CLKOUT1 Clock Output Generated from
Input Clock (1 if CLKSEL = 1
or /2 if CLKSEL = 0)
Various Pins
1 AUX_ADC_A1 Auxiliary ADC A Input 1
3, 4, 13 AVDD Analog Power Pins
2, 9 AGND Analog Ground Pins
5 SIGDELT Digital Output from
Programmable Sigma-Delta
6 AUX_DAC_A Auxiliary DAC A Output
7 AUX_DAC_B Auxiliary DAC B Output
8 AUX_DAC_C Auxiliary DAC C Output
33, 36, 53, DVDD Digital Power Supply Pin
59, 61, 66,
93
34, 35, 52, DGND Digital Ground Pin
58, 60, 67,
94
54 SCLK Serial Bus Clock Input
55 SDO Serial Bus Data Bit
56 SDIO Serial Bus Data Bit
57 SEN Serial Bus Enable
63 RESETB Reset (SPI Registers and Logic)
95 AUX_SPI_do Optional Auxiliary ADC Serial Bus
Data Out Bit
96 AUX_SPI_clk Optional Auxiliary ADC Serial Bus
Data Out Latch Clock
97 AUX_SPI_csb Optional Auxiliary ADC Serial Bus
Chip Select Bit
128 AUX_ADC_A2 Auxiliary ADC A Input 2
126 AUX_ADC_B1 Auxiliary ADC B Input 1
125 AUX_ADC_B2 Auxiliary ADC B Input 2
127 AUX_ADC_REF Auxiliary ADC Reference
Pin No. Mnemonic Function
Receive Pins
68/7079 D0A to 10-/12-Bit ADC Output of
D9A/D11A Receive Channel A
80/8291 D0B to 10-/12-Bit ADC Output of
D9B/D11B Receive Channel B
92 RxSYNC Synchronization Clock for
Channel A and Channel B Rx Paths
98, 99, AVDD Analog Supply Pins
104, 105,
117, 118,
123, 124,
100, 103, AGND Analog Ground Pins
106, 109,
110, 112,
113, 116,
119, 122,
101 REFT_B Top Reference Decoupling for
Channel B ADC
102 REFB_B Bottom Reference Decoupling
for Channel B ADC
107 VIN+B Receive Channel B Differential (+) Input
108 VINB Receive Channel B Differential (
) Input
111 VREF Internal ADC Voltage Reference
114 VINA Receive Channel A Differential (
) Input
115 VIN+A Receive Channel A Differential (+) Input
120 REFB_A Bottom Reference Decoupling for
Channel A ADC
121 REFT_A Top Reference Decoupling for
Channel A ADC
Transmit Pins
18, 20 AVDD Analog Supply Pins
23, 32
19, 24, AGND Analog Ground Pins
27, 28, 31
21 REFIO Reference Output, 1.2 V Nominal
22 FSADJ Full-Scale Current Adjust
25 IOUTATransmit Channel A DAC
Differential (
) Output
26 IOUT+A Transmit Channel A DAC
Differential (+) Output
29 IOUT+B Transmit Channel B DAC
Differential (+) Output
30 IOUTBTransmit Channel B DAC
Differential (
) Output
3748/50 Tx11/Tx13 12-/14-Bit Transmit DAC Data
to Tx0 (Interleaved Data when Required)
51 TxSYNC Synchronization Input for Transmitter
62 MODE/ Configures Default Timing Mode,
TxBLANK* Controls Tx Digital Power Down
*The logic level of the Mode/TxBLANK pin at power up defines the default timing
mode; a logic low configures Normal Operation, logic high configures Alternate
Operation Mode.
PIN FUNCTION DESCRIPTIONS
REV. 0–8–
AD9860/AD9862
DEFINITIONS OF SPECIFICATIONS
Differential Nonlinearity Error (DNL, No Missing Codes)
An ideal converter exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed no
missing codes to 10-bit resolution indicate that all 1024 codes
respectively, must be present over all operating ranges.
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code from
a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
Phase Noise
Single-sideband phase noise power is specified relative to the
carrier (dBc/Hz) at a given frequency offset (1 kHz) from the
carrier. Phase noise can be measured directly in Single Tone Trans-
mit Mode with a spectrum analyzer that supports noise marker
measurements. It detects the relative power between the carrier
and the offset (1 kHz) sideband noise and takes the resolution
bandwidth (rbw) into account by subtracting 10 log(rbw). It also
adds a correction factor that compensates for the implementation
of the resolution bandwidth, log display, and detector characteristic.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Spurious-Free Dynamic Range (SFDR)
The difference, in dB, between the rms amplitude of the DACs
output signal (or ADCs input signal) and the peak spurious
signal over the specified bandwidth (Nyquist bandwidth unless
otherwise noted).
Pipeline Delay (Latency)
The number of clock cycles between conversion initiation and
the associated output data being made available.
Offset Error
First transition should occur for an analog value 1/2 LSB above
full scale. Offset error is defined as the deviation of the actual
transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above full scale. The last transition should occur for an analog
value 1 1/2 LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Aperture Delay
The aperture delay is a measure of the Sample-and-Hold Ampli-
fier (SHA) performance and specifies the time delay between the
rising edge of the sampling clock input to when the input signal
is held for conversion.
Aperture Uncertainty (Jitter)
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the ADC.
Input Referred Noise
The rms output noise is measured using histogram techniques.
The ADC output codes standard deviation is calculated in LSB
and converted to an equivalent voltage. This results in a noise
figure that can be referred directly to the input of the AD9860/
AD9862.
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number
of bits. Using the following formula:
N =
()
SINAD dB .
.
176
602
it is possible to get a measure of performance expressed as N,
the effective number of bits. Thus, effective number of bits for
a device for sine wave inputs at a given input frequency can be
calculated directly from its measured SINAD.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
Power Supply Rejection
Power supply rejection specifies the converters maximum full-scale
change when the supplies are varied from nominal to minimum
and maximum specified voltages.
Channel-to-Channel Isolation (Crosstalk)
In an ideal multichannel system, the signal in one channel will
not influence the signal level of another channel. The channel-
to-channel isolation specification is a measure of the change that
occurs to a grounded channel as a full-scale signal is applied to
another channel.
REV. 0
Typical Performance Characteristics–AD9860/AD9862
–9–
FREQUENCY – MHz
0
MAGNITUDE – dBm
0
–20
–40
20 40 60 80 100 110 120
–60
–80
–100
140
–90
–70
–50
–30
–10
f
DATA
= 32MSPS
4 INTERPOLATION
TPC 1. AD9862 Tx Output 6 MHz
Single Tone; CLKIN = 32 MHz;
DLL 4
Setting
FREQUENCY – MHz
0
MAGNITUDE – dBm
0
–20
–40
20 40
60
80 100 110 120
–60
–80
–100
140
–120
f
DATA
= 32MSPS
1 INTERPOLATION
TPC 4. TxDAC Generating an
OFDM Signal; CLKIN = 64 MHz,
DLL 2
Setting
f
OUT
– MHz
52035
–60
–65
–70
–75
–80
–85
–90
10
15 25 30
THD – dBc
f
DATA
= 64MSPS
2 INTERPOLATION
THD
2nd
3rd
TPC 7. TxDAC Harmonic
Distortion vs. f
OUT
FREQUENCY – MHz
0
MAGNITUDE – dBm
0
–20
–40
20 40
60
80 100 110 120
–60
–80
–100
140
–90
–70
–50
–30
–10
f
DATA
= 32MSPS
4 INTERPOLATION
TPC 2. AD9862 Tx Output 6 MHz
Single Tone; CLKIN = 64 MHz;
DLL 2
Setting
FREQUENCY – MHz
0
MAGNITUDE – dBm
0
–20
–40
20 40 60 80 100 110 120
–60
–80
–100
140
–120
f
DATA
= 32MSPS
4 INTERPOLATION
TPC 5. TxDAC Generating an
OFDM Signal; CLKIN = 64 MHz,
DLL 2
Setting
FREQUENCY
– MHz
5
SNR – dB
20
74
10 15 25 30
73
72
71
70
69
68
0
f
DATA
= 64MSPS
2 INTERPOLATION
AD9862
AD9860
TPC 8. Signal-to-Noise Ratio (SNR)
vs. f
OUT
FREQUENCY – MHz
0
MAGNITUDE – dBm
0
–20
–40
20 40
60
80 100 110 120
–60
–80
–100
140
–90
–70
–50
–30
–10
f
DATA
= 32MSPS
4 INTERPOLATION
TPC 3. AD9862 Tx Output 6 MHz
Single Tone; CLKIN = 128 MHz;
DLL 1
Setting
FREQUENCY – MHz
7.90
MAGNITUDE – dBm
0
–20
–40
–60
–80
–100
–120
7.92 7.94 7.96 7.98 8.00 8.02 8.04 8.06 8.08
f
DATA
= 32MSPS
4 INTERPOLATION
TPC 6. Zoomed in Plot of Four
Notched Carriers of OFDM Signal;
CLKIN = 64 MHz, DLL 2
Setting
CARRIER FREQUENCY – MHz
5
IMD – dBc
20
–60
–65
–70
–75
–80
–85
–90
10 15 25 30
–50
–55
–95
AV DD = 3.0V
AV DD = 3.3V
AV DD = 3.6V
f
DATA
= 64MSPS
2 INTERPOLATION
TPC 9. Two Tone Intermodulation
vs. f
OUT1
(f
OUT2
= f
OUT1
+ 1 MHz)

AD9862BSTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE Mixed Signal Front-End Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union