I
DD
Specifications
Table 10: DDR2 I
DD
Specifications and Conditions – 2GB (Die Revision G)
Values shown for MT47H1286M4 DDR2 SDRAM only and are computed from values specified in the 512Mb (128 Meg x 4)
component data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
DD0
1
1296 1206 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4, CL =
CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD
(I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as I
DD4W
I
DD1
1
1476 1386 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
I
DD2P
2
252 252 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
I
DD2Q
2
864 792 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is HIGH, S#
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
I
DD2N
2
1008 900 mA
Active power-down current: All device banks open;
t
CK =
t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
2
648 540 mA
Slow PDN exit
MR[12] = 1
324 324
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX
(I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
I
DD3N
2
1188 1080 mA
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
I
DD4W
1
2376 2196 mA
Operating burst read current: All device banks open; Continuous burst read, I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP
(I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
I
DD4R
1
2286 2106 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
) inter-
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
I
DD5
2
1836 1746 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
I
DD6
2
252 252 mA
2Gb, 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
I
DD
Specifications
PDF: 09005aef83d65c27
htf36c256_512_1gx72pz.pdf - Rev. E 4/14 EN
10
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