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MT36HTF1G72PZ-80EC1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
Table 15: PLL Specifications
CU877 device or equivalent
Parameter Symbol Pins Condition Min Max Units
DC high-level
input voltage
V
IH
RESET# LVCMOS 0.65 × V
DD
– V
DC low-level
input voltage
V
IL
RESET# LVCMOS – 0.35 × V
DD
V
Input voltage (limits) V
IN
RESET#, CK,
CK#
– - 0.3 V
DD
+ 0.3 V
DC high-level
input voltage
V
IH
CK, CK# Differential input 0.65 × V
DD
– V
DC low-level
input voltage
V
IL
CK, CK# Differential input – 0.35 × V
DD
V
Input differential-pair
cross voltage
V
IX
CK, CK# Differential input (V
DDQ
/2) - 0.15 (V
DD
/2) + 0.15 V
Input differential
voltage
V
ID(DC)
CK, CK# Differential input 0.3 V
DD
+ 0.4 V
Input differential
voltage
V
ID(AC)
CK, CK# Differential input 0.6 V
DD
+ 0.4 V
Input current I
I
RESET# V
I
= V
DD
or V
SS
–10 10 µA
CK, CK# V
I
= V
DD
or V
SS
–250 250 µA
Output disabled
current
I
ODL
RESET# = V
SS
; V
I
= V
IH(AC)
or V
IL(DC)
100 – µA
Static supply current I
DDLD
CK = CK# = LOW – 500 µA
Dynamic supply I
DD
N/A CK, CK# = 270 MHz, all
outputs open (not con-
nected to PCB)
– 300 mA
Input capacitance C
IN
Each input V
I
= V
DD
or V
SS
2 3 pF
Table 16: PLL Clock Driver Timing Requirements and Switching Characteristics
Parameter Symbol Min Max Units
Stabilization time
t
L – 15 μs
Input clock slew rate slr(i) 1.0 4.0 V/ns
SSC modulation frequency – 30 33 kHz
SSC clock input frequency deviation – 0.0 –0.5 %
PLL loop bandwidth (–3dB from unity gain) – 2.0 – MHz
Note:
1. PLL timing and switching specifications are critical for proper operation of the DDR2
DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information
is available in JEDEC standard JESD82.
2Gb, 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Register and PLL Specifications
PDF: 09005aef83d65c27
htf36c256_512_1gx72pz.pdf - Rev. E 4/14 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 17: SPD EEPROM Operating Conditions
Parameter/Condition Symbol Min Max Units
Supply voltage V
DDSPD
1.7 3.6 V
Input high voltage: logic 1; All inputs V
IH
V
DDSPD
× 0.7 V
DDSPD
+ 0.5 V
Input low voltage: logic 0; All inputs V
IL
–0.6 V
DDSPD
× 0.3 V
Output low voltage: I
OUT
= 3mA V
OL
– 0.4 V
Input leakage current: V
IN
= GND to V
DD
I
LI
0.1 3 µA
Output leakage current: V
OUT
= GND to V
DD
I
LO
0.05 3 µA
Standby current I
SB
1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz I
CCR
0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz I
CCW
2 3 mA
Table 18: SPD EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time bus must be free before a new transition can start
t
BUF 1.3 – µs
Data-out hold time
t
DH 200 – ns
SDA and SCL fall time
t
F – 300 ns 2
SDA and SCL rise time
t
R – 300 ns 2
Data-in hold time
t
HD:DAT 0 – µs
Start condition hold time
t
HD:STA 0.6 – µs
Clock HIGH period
t
HIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs
t
I – 50 ns
Clock LOW period
t
LOW 1.3 – µs
SCL clock frequency
t
SCL – 400 kHz
Data-in setup time
t
SU:DAT 100 – ns
Start condition setup time
t
SU:STA 0.6 – µs 3
Stop condition setup time
t
SU:STO 0.6 – µs
WRITE cycle time
t
WRC – 10 ms 4
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to
pull-up resistance, and the EEPROM does not respond to its slave address.
2Gb, 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
PDF: 09005aef83d65c27
htf36c256_512_1gx72pz.pdf - Rev. E 4/14 EN
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Module Dimensions
Figure 3: 240-Pin DDR2 RDIMM
Pin 1
17.78 (0.7)
TYP
2.5 (0.098) D
(2X)
2.3 (0.091) TYP
5.0 (0.197) TYP
123.0 (4.840)
TYP
1.0 (0.039)
TYP
0.8 (0.031)
TYP
2.0 (0.079) R
(4X)
0.76 (0.03) R
Pin 120
Front view
133.5 (5.256)
133.2 (5.244)
63.0 (2.48)
TYP
55.0 (2.165)
TYP
10.0 (0.394)
TYP
Back view
Pin 240
Pin 121
1.37 (0.054)
1.17 (0.046)
4.0 (0.157)
MAX
70.66 (2.782)
TYP
2.21 (0.087) TYP
3.04 (0.1197)
TYP
1.0 (0.039) TYP
30.5 (1.2)
29.85 (1.175)
45° (4X)
U1
U12
U2
U13
U3 U4
U14 U15
U5
U16
U7
U6
U17
U8 U9
U18 U19
U10 U11
U20 U21
U22 U23
U32 U33
U24
U34
U25
U35
U26
U27
U36
U28
U37
U29 U30
U38 U39
U31
U40
Notes:
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
2Gb, 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Module Dimensions
PDF: 09005aef83d65c27
htf36c256_512_1gx72pz.pdf - Rev. E 4/14 EN
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

MT36HTF1G72PZ-80EC1

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Memory Modules DDR2 8GB RDIMM
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