MT36HTF1G72PZ-80EC1 Datasheet MT36HTF1G72PZ-80EC1, MT36HTF51272PZ-667H1, MT36HTF1G72PZ-667C1 | P13-P15

Table 12: DDR2 I

DD

Specifications and Conditions – 4GB (Die Revisions M) (Continued)

Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) com-

ponent data sheet

Parameter Symbol

-80E/

-800 -667 Units

Active power-down current: All device banks open;

t

CK =

t

CK

(I

DD

); CKE is LOW; Other control and address bus inputs are stable;

Data bus inputs are floating

Fast PDN exit

MR[12] = 0

I

DD3P

2

1008 1008 mA

Slow PDN exit

MR[12] = 1

720 720

Active standby current: All device banks open;

t

CK =

t

CK (I

DD

),

t

RAS =

t

RAS MAX

(I

DD

),

t

RP =

t

RP (I

DD

); CKE is HIGH, S# is HIGH between valid commands; Other con-

trol and address bus inputs are switching; Data bus inputs are switching

I

DD3N

2

1188 1080 mA

Operating burst write current: All device banks open; Continuous burst writes;

BL = 4, CL = CL (I

DD

), AL = 0;

t

CK =

t

CK (I

DD

),

t

RAS =

t

RAS MAX (I

DD

),

t

RP =

t

RP (I

DD

);

CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;

Data bus inputs are switching

I

DD4W

1

2430 2250 mA

Operating burst read current: All device banks open; Continuous burst read, I

OUT

= 0mA; BL = 4, CL = CL (I

DD

), AL = 0;

t

CK =

t

CK (I

DD

),

t

RAS =

t

RAS MAX (I

DD

),

t

RP =

t

RP

(I

DD

); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are

switching; Data bus inputs are switching

I

DD4R

1

2340 2160 mA

Burst refresh current:

t

CK =

t

CK (I

DD

); REFRESH command at every

t

RFC (I

DD

) inter-

val; CKE is HIGH, S# is HIGH between valid commands; Other control and address

bus inputs are switching; Data bus inputs are switching

I

DD5

2

2970 2880 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus

inputs are floating; Data bus inputs are floating

I

DD6

2

252 252 mA

Operating bank interleave read current: All device banks interleaving reads,

I

OUT

= 0mA; BL = 4, CL = CL (I

DD

), AL =

t

RCD (I

DD

) - 1 ×

t

CK (I

DD

);

t

CK =

t

CK (I

DD

),

t

RC =

t

RC (I

DD

),

t

RRD =

t

RRD (I

DD

),

t

RCD =

t

RCD (I

DD

); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are stable during deselects; Data bus inputs are

switching

I

DD7

1

3960 3510 mA

Notes:

1. Value calculated as one module rank in this operating condition. All other module ranks

in I

DD2P

(CKE LOW) mode.

2. Value calculated reflects all module ranks in this operating condition.

Table 13: DDR2 I

DD

Specifications and Conditions – 8GB (Die Revision C)

Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb (512 Meg x 4) com-

ponent data sheet

Parameter Symbol

-80E/

-800 -667 Units

Operating one bank active-precharge current:

t

CK =

t

CK (I

DD

),

t

RC =

t

RC (I

DD

),

t

RAS =

t

RAS MIN (I

DD

); CKE is HIGH, S# is HIGH between valid commands; Address

bus inputs are switching; Data bus inputs are switching

I

DD0

1

1566 1476 mA

Operating one bank active-read-precharge current: I

OUT

= 0mA; BL = 4, CL =

CL (I

DD

), AL = 0;

t

CK =

t

CK (I

DD

),

t

RC =

t

RC (I

DD

),

t

RAS =

t

RAS MIN (I

DD

),

t

RCD =

t

RCD

(I

DD

); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are

switching; Data pattern is same as I

DD4W

I

DD1

1

1764 1656 mA

2Gb, 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM

I

DD

Specifications

PDF: 09005aef83d65c27

htf36c256_512_1gx72pz.pdf - Rev. E 4/14 EN

13

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 13: DDR2 I

DD

Specifications and Conditions – 8GB (Die Revision C) (Continued)

Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb (512 Meg x 4) com-

ponent data sheet

Parameter Symbol

-80E/

-800 -667 Units

Precharge power-down current: All device banks idle;

t

CK =

t

CK (I

DD

); CKE is

LOW; Other control and address bus inputs are stable; Data bus inputs are floating

I

DD2P

2

432 432 mA

Precharge quiet standby current: All device banks idle;

t

CK =

t

CK (I

DD

); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs

are floating

I

DD2Q

2

1080 900 mA

Precharge standby current: All device banks idle;

t

CK =

t

CK (I

DD

); CKE is HIGH, S#

is HIGH; Other control and address bus inputs are switching; Data bus inputs are

switching

I

DD2N

2

1260 1080 mA

Active power-down current: All device banks open;

t

CK =

t

CK

(I

DD

); CKE is LOW; Other control and address bus inputs are stable;

Data bus inputs are floating

Fast PDN exit

MR[12] = 0

I

DD3P

2

900 900 mA

Slow PDN exit

MR[12] = 1

504 504

Active standby current: All device banks open;

t

CK =

t

CK (I

DD

),

t

RAS =

t

RAS MAX

(I

DD

),

t

RP =

t

RP (I

DD

); CKE is HIGH, S# is HIGH between valid commands; Other con-

trol and address bus inputs are switching; Data bus inputs are switching

I

DD3N

2

1800 1620 mA

Operating burst write current: All device banks open; Continuous burst writes;

BL = 4, CL = CL (I

DD

), AL = 0;

t

CK =

t

CK (I

DD

),

t

RAS =

t

RAS MAX (I

DD

),

t

RP =

t

RP (I

DD

);

CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;

Data bus inputs are switching

I

DD4W

1

2556 2196 mA

Operating burst read current: All device banks open; Continuous burst read, I

OUT

= 0mA; BL = 4, CL = CL (I

DD

), AL = 0;

t

CK =

t

CK (I

DD

),

t

RAS =

t

RAS MAX (I

DD

),

t

RP =

t

RP

(I

DD

); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are

switching; Data bus inputs are switching

I

DD4R

1

2556 2196 mA

Burst refresh current:

t

CK =

t

CK (I

DD

); REFRESH command at every

t

RFC (I

DD

) inter-

val; CKE is HIGH, S# is HIGH between valid commands; Other control and address

bus inputs are switching; Data bus inputs are switching

I

DD5

2

3276 3186 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus

inputs are floating; Data bus inputs are floating

I

DD6

2

432 432 mA

Operating bank interleave read current: All device banks interleaving reads,

I

OUT

= 0mA; BL = 4, CL = CL (I

DD

), AL =

t

RCD (I

DD

) - 1 ×

t

CK (I

DD

);

t

CK =

t

CK (I

DD

),

t

RC =

t

RC (I

DD

),

t

RRD =

t

RRD (I

DD

),

t

RCD =

t

RCD (I

DD

); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are stable during deselects; Data bus inputs are

switching

I

DD7

1

4176 3816 mA

Notes:

1. Value calculated as one module rank in this operating condition. All other module ranks

in I

DD2P

(CKE LOW) mode.

2. Value calculated reflects all module ranks in this operating condition.

2Gb, 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM

I

DD

Specifications

PDF: 09005aef83d65c27

htf36c256_512_1gx72pz.pdf - Rev. E 4/14 EN

14

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Register and PLL Specifications

Table 14: Register Specifications

SSTU32866 devices or equivalent

Parameter Symbol Pins Condition Min Max Units

DC high-level

input voltage

V

IH(DC)

Control, command,

address

SSTL_18 V

REF(DC)

+ 125 V

DDQ

+ 250 mV

DC low-level

input voltage

V

IL(DC)

Control, command,

address

SSTL_18 0 V

REF(DC)

- 125 mV

AC high-level

input voltage

V

IH(AC)

Control, command,

address

SSTL_18 V

REF(DC)

+ 250 – mV

AC low-level

input voltage

V

IL(AC)

Control, command,

address

SSTL_18 – V

REF(DC)

- 250 mV

Output high

voltage

V

OH

Parity output LVCMOS 1.2 – V

Output low voltage V

OL

Parity output LVCMOS – 0.5 V

Input current I

I

All pins V

I

= V

DD

or V

SS

– ±0.5 µA

Static standby I

DD

All pins RESET# = V

SSQ

(I

O

= 0) – 100 µA

Static operating I

DD

All pins RESET# = V

SS

; V

I

= V

IH(AC)

or V

IL(DC)

I

O

= 0

– 40 mA

Dynamic operating

(clock tree)

I

DDD

N/A RESET# = V

DD

;

V

I

= V

IH(DC)

or V

IL(AC)

,

I

O

= 0; CK and CK#

switching 50% duty cy-

cle

– Varies by

manufacturer

µA

Dynamic operating

(per each input)

I

DDD

N/A RESET# = V

DD

;

V

I

= V

IH(AC)

or V

IL(DC)

,

I

O

= 0; CK and CK#

switching 50% duty

cycle; One data in/out

switching at

t

CK/2,

50% duty cycle

– Varies by

manufacturer

µA

Input capacitance

(per device, per pin)

C

IN

All inputs except

RESET#

V

I

= V

REF

±250mV;

V

DD

= 1.8V

2.5 3.5 pF

Input capacitance

(per device, per pin)

C

IN

RESET# V

I

= V

DD

or V

SS

Varies by

manufacturer

Varies by

manufacturer

pF

Note:

1. Timing and switching specifications for the register listed are critical for proper opera-

tion of the DDR2 SDRAM RDIMMs. These are meant to be a subset of the parameters for

the specific device used on the module. Detailed information for this register is available

in JEDEC standard JESD82.

2Gb, 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM

Register and PLL Specifications

PDF: 09005aef83d65c27

htf36c256_512_1gx72pz.pdf - Rev. E 4/14 EN

15

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT36HTF1G72PZ-80EC1

MT36HTF1G72PZ-80EC1

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