REV. E
AD7703
–9–
Table II. Resonator Loading Capacitors
Resonators C1 (pF) C2 (pF)
Ceramic
200 kHz 330 470
455 kHz 100 100
1.0 MHz 50 50
2.0 MHz 20 20
Crystal
2.000 MHz 30 30
3.579 MHz 20 20
4.096 MHz None None
The input sampling frequency, output data rate, filter character-
istics, and calibration time are all directly related to the master
clock frequency, f
CLKIN
, by the ratios given in the Specification
table under Dynamic Performance. Therefore, the first step in
system design with the AD7703 is to select a master clock fre-
quency suitable for the bandwidth and output data rate required
by the application.
ANALOG INPUT RANGES
The AD7703 performs conversion relative to an externally
supplied reference voltage that allows easy interfacing to ratio-
metric systems. In addition, either unipolar or bipolar input
voltage ranges may be selected using the BP/UP input. With
BP/UP tied low, the input range is unipolar and the span is
(V
REF
to V
AGND
), where V
AGND
is the voltage at the device AGND
pin. With BP/UP tied high, the input range is bipolar and the
span is 2V
REF
. In the Bipolar mode, both positive and negative
full scale are directly determined by V
REF
. This offers superior
tracking of positive and negative full scale and better midscale
(bipolar zero) stability than bipolar schemes that simply scale
and offset the input range.
The digital output coding for the unipolar range is unipolar binary;
for the bipolar range it is offset binary. Bit weights for the Unipolar
and Bipolar modes are shown in Table I.
ACCURACY
S-D ADCs, like VFCs and other integrating ADCs, do not
contain any source of nonmonotonicity and inherently offer
no-missing-codes performance.
The AD7703 achieves excellent linearity by the use of high
quality, on-chip silicon dioxide capacitors, which have a very
low capacitance/voltage coefficient. The device also achieves low
input drift through the use of chopper-stabilized techniques in
its input stage. To ensure excellent performance over time and
temperature, the AD7703 uses digital calibration techniques
that minimize offset and gain error to typically ±4 LSB.
AUTOCALIBRATION
The AD7703 offers both self-calibration and system-calibration
facilities. For calibration to occur, the on-chip microcontroller
must record the modulator output for two different input condi-
tions. These are the zero-scale and full-scale points. In Unipolar
self-calibration mode, the zero-scale point is V
AGND
and the
full-scale point is V
REF
. With these readings, the microcontroller
can calculate the gain slope for the input to output transfer
function of the converter. In Unipolar mode, the slope factor is
determined by dividing the span between zero and full scale by
2
20
. In Bipolar mode, it is determined by dividing the span by
2
19
since the inputs applied represent only half the total codes.
In both Unipolar and Bipolar modes, the slope factor is saved
and used to calculate the binary output code when an analog
input is applied to the device. Table IV gives the output code
size after calibration.
System calibration allows the AD7703 to compensate for system
gain and offset errors. A typical circuit where this might be used
is shown in Figure 12.
System calibration performs the same slope factor calculations
as self-calibration but uses voltage values presented by the system
to the A
IN
pin for the zero- and full-scale points. There are two
system calibration modes.
The first mode offers system level calibration for system offset
and system gain. This is a two step operation. The zero-scale
point must be presented to the converter first. It must be applied
to the converter before the calibration step is initiated and remain
stable until the step is complete. The DRDY output from the
device will signal when the step is complete by going low. After
the zero-scale point is calibrated, the full-scale point is applied
and the second calibration step is initiated. Again, the voltage
must remain stable throughout the calibration step.
The two step calibration mode offers another feature. After the
sequence has been completed, additional offset calibrations can be
performed by themselves to adjust the zero reference point to a
new system zero reference value. This second system calibration
mode uses an input voltage for the zero-scale calibration point
but uses the V
REF
value for the full-scale point.
SYSTEM
REF HI
A
IN
SYSTEM
REF LO
ANALOG
MUX
A0
A1
SIGNAL
CONDITIONING
AD7703
SCLK
SDATA
CAL
SC1
SC2
MICRO-
COMPUTER
A
IN
Figure 12. Typical Connections for System Calibration
