AD7703AN Datasheet AD7703CNZ, AD7703CRZ, AD7703ARZ | P7-P9

REV. E–6–

AD7703

PIN CONFIGURATION

DIP, CERDIP, SOIC

MODE

SC1

DGND

CLKOUT

CLKIN

AGND

REF

SDATA

SCLK

SC2

CAL

DRDY

BP/UP

SLEEP

TOP VIEW

(Not to Scale)

AD7703

Table I. Bit Weight Table (2.5 V Reference Voltage)

Unipolar Mode Bipolar Mode

ppm ppm

␮V LSB % FS FS LSB % FS FS

0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12

1.192 0.5 0.0000477 0.48 0.26 0.0000238 0.24

2.384 1.00 0.0000954 0.95 0.5 0.0000477 0.48

4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95

9.537 4.00 0.0003814 3.81 2.00 0.0001907 1.91

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 MODE Selects the Serial Interface Mode. If MODE is tied to DGND, the Synchronous External Clocking (SEC)

mode is selected. SCLK is configured as an input, and the output appears without formatting, the MSB

coming first. If MODE is tied to +5 V, the AD7703 operates in the Synchronous Self-Clocking (SSC) mode.

SCLK is configured as an output, with a clock frequency for f

CLKIN

/4 and 25% duty cycle.

2 CLKOUT Clock Output to Generate an Internal Master Clock by Connecting a Crystal between CLKOUT and CLKIN.

If an external clock is used, CLKOUT is not connected.

3 CLKIN Clock Input for External Clock.

4, 17 SC1, SC2 System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration

performed.

5 DGND Digital Ground. Ground reference for all digital signals.

6DV

Digital Negative Supply, –5 V Nominal.

7AV

Analog Negative Supply, –5 V Nominal.

8 AGND Analog Ground. Ground reference for all analog signals.

Analog Input.

10 V

REF

Voltage Reference Input, 2.5 V Nominal. This determines the value of positive full scale in the Unipolar

mode and the value of both positive and negative full scale in the Bipolar mode.

11 SLEEP Sleep Mode Pin. When this pin is taken low, the AD7703 goes into a low power mode with typically 10 µW

power consumption.

12 BP/UP Bipolar/Unipolar Mode Pin. When this pin is low, the AD7703 is configured for a unipolar input range going

from AGND to V

REF

. When Pin 12 is high, the AD7703 is configured for a bipolar input range, ±V

REF

13 CAL Calibration Mode Pin. When CAL is taken high for more than four cycles, the AD7703 is reset and performs

a calibration cycle when CAL is brought low again. The CAL pin can also be used as a strobe to synchronize

the operation of several AD7703s.

14 AV

Analog Positive Supply, 5 V Nominal.

15 DV

Digital Positive Supply, 5 V Nominal.

16 CS Chip Select Input. When CS is brought low, the AD7703 will begin to transmit serial data in a format determined

by the state of the MODE pin.

18 DRDY Data Ready Output. DRDY is low when valid data is available in the output register. It goes high after trans-

mission of a word is completed. It also goes high for four clock cycles when a new data-word is being loaded

into the output register, to indicate that valid data is not available, irrespective of whether data transmission

is complete or not.

19 SCLK Serial Clock Input/Output. The SCLK pin is configured as an input or output, dependent on the type of

serial data transmission that has been selected by the MODE pin. When configured as an output in the

Synchronous Self-Clocking mode, it has a frequency of f

CLKIN

/4 and a duty cycle of 25%.

20 SDATA Serial Data Output. The AD7703’s output data is available at this pin as a 20-bit serial word.

REV. E

AD7703

–7–

GENERAL DESCRIPTION

The AD7703 is a 20-bit A/D converter with on-chip digital

filtering, intended for the measurement of wide dynamic range,

low frequency signals such as those representing chemical,

physical, or biological processes. It contains a charge-balancing

(⌺-⌬) ADC, calibration microcontroller with on-chip static

RAM, clock oscillator, and serial communications port.

The analog input signal to the AD7703 is continuously sampled

at a rate determined by the frequency of the master clock, CLKIN.

A charge-balancing A/D converter (⌺-⌬ modulator) converts

the sampled signal into a digital pulse train whose duty cycle

contains the digital information. A six-pole Gaussian digital

low-pass filter processes the output of the ⌺-⌬ modulator and

updates the 20-bit output register at a 4 kHz rate. The output

data can be read from the serial port randomly or periodically at

any rate up to 4 kHz.

AD7703

MODE

SDATA

SC1

DGND

CLKOUT

CLKIN

AGND

SCLK

SC2

CAL

BP/UP

SLEEP

RANGE

SELECT

CALIBRATE

ANALOG

INPUT

ANALOG

GROUND

–5V

ANALOG

SUPPLY

0.1␮F

+5V

ANALOG

SUPPLY

2.5V

0.1␮F

DRDY

0.1␮F

10␮F

REF

VOLTAG E

REFERENCE

10␮F

DATA READY

READ

(TRANSMIT)

SERIAL CLOCK

SERIAL DATA

Figure 7. Typical System Connection Diagram

The AD7703 can perform self-calibration using the on-chip

calibration microcontroller and SRAM to store calibration

parameters. A calibration cycle may be initiated at any time

using the CAL control input.

Other system components may also be included in the calibra-

tion loop to remove offset and gain errors in the input channel.

For battery operation, the AD7703 also offers a standby mode

that reduces idle power consumption to typically 10 µW.

THEORY OF OPERATION

The general block diagram of a ⌺-⌬ ADC is shown in Figure 8.

It contains the following elements:

1. A sample-hold amplifier

2. A differential amplifier or subtracter

3. An analog low-pass filter

4. A 1-bit A/D converter (comparator)

5. A 1-bit DAC

6. A digital low-pass filter

ANALOG

LOW-PASS

FILTER

COMPARATOR

DIGITAL DATA

S/H AMP

DAC

DIGITAL

FILTER

Figure 8. General

⌺

⌬

ADC

In operation, the analog signal sample is fed to the subtracter,

along with the output of the 1-bit DAC. The filtered difference

signal is fed to the comparator, whose output samples the differ-

ence signal at a frequency many times that of the analog signal

sampling frequency (oversampling).

Oversampling is fundamental to the operation of ⌺-⌬ ADCs.

Using the quantization noise formula for an ADC

SNR = (6.02 ¥ number of bits + 1.76) dB

a 1-bit ADC or comparator yields an SNR of 7.78 dB.

The AD7703 samples the input signal at 16 kHz, which spreads

the quantization noise from 0 kHz to 8 kHz. Since the specified

analog input bandwidth of the AD7703 is only 0 Hz to 10 Hz, the

noise energy in this bandwidth would be only 1/800 of the total

quantization noise, even if the noise energy were spread evenly

throughout the spectrum. It is reduced still further by analog

filtering in the modulator loop, which shapes the quantization

noise spectrum to move most of the noise energy to frequencies

above 10 Hz. The SNR performance in the 0 Hz to 10 Hz range

is conditioned to the 20-bit level in this fashion.

The output of the comparator provides the digital input for the

1-bit DAC, so the system functions as a negative feedback loop

that minimizes the difference signal. The digital data that repre-

sents the analog input voltage is in the duty cycle of the pulse train

appearing at the output of the comparator. It can be retrieved as

a parallel binary data-word using a digital filter.

⌺-⌬ ADCs are generally described by the order of the analog

low-pass filter. A simple example of a first-order, ⌺-⌬ ADC is

shown in Figure 8. This contains only a first-order, low-pass

filter or integrator. It also illustrates the derivation of the alter-

native name for these devices: charge-balancing ADCs.

The AD7703 uses a second-order, ⌺-⌬ modulator and a sophis-

ticated digital filter that provides a rolling average of the sampled

output. After power-up or if there is a step change in the input

voltage, there is a settling time that must elapse before valid

data is obtained.

REV. E–8–

AD7703

DIGITAL FILTERING

The AD7703’s digital filter behaves like an analog filter, with a

few minor differences.

First, since digital filtering occurs after the analog-to-digital

conversion, it can remove noise injected during the conversion

process. Analog filtering cannot do this.

On the other hand, analog filtering can remove noise superim-

posed on the analog signal before it reaches the ADC. Digital

filtering cannot do this and noise peaks riding on signals near

full scale have the potential to saturate the analog modulator and

digital filter, even though the average value of the signal is within

limits. To alleviate this problem, the AD7703 has overrange

headroom built into the ⌺-⌬ modulator and digital filter that

allows overrange excursions of 100 mV. If noise signals are larger

than this, consideration should be given to analog input filtering,

or to reducing the gain in the input channel so that a full-scale

input (2.5 V) gives only a half-scale input to the AD7703 (1.25 V).

This will provide an overrange capability greater than 100% at

the expense of reducing the dynamic range by one bit (50%).

FILTER CHARACTERISTICS

The cutoff frequency of the digital filter is f

CLK

/409600. At the

maximum clock frequency of 4.096 MHz, the cutoff frequency

of the filter is 10 Hz and the data update rate is 4 kHz.

Figure 9 shows the filter frequency response. This is a six-pole

Gaussian response that provides 55 dB of 60 Hz rejection for a

10 Hz cutoff frequency. If the clock frequency is halved to give a

5 Hz cutoff, 60 Hz rejection is better than 90 dB.

100

FREQUENCY – Hz

–20

–40

–60

–80

–100

–120

–140

–160

GAIN – dB

CLK

= 1MHz

CLK

= 2MHz

CLK

= 4MHz

Figure 9. Frequency Response of AD7703 Filter

Since the AD7703 contains this low-pass filtering, there is a

settling time associated with step function inputs, and data will

be invalid after a step change until the settling time has elapsed.

The AD7703 is, therefore, unsuitable for high speed multiplex-

ing, where channels are switched and converted sequentially at

high rates, as switching between channels can cause a step change

in the input. However, slow multiplexing of the AD7703 is

possible, provided that the settling time is allowed to elapse

before data for the new channel is accessed.

The output settling of the AD7703 in response to a step input

change is shown in Figure 10. The Gaussian response has fast

settling with no overshoot, and the worst-case settling time to

±0.0007% is 125 ms with a 4.096 MHz master clock frequency.

PERCENT OF FINAL VALUE

100

04080120 160

TIME – ms

Figure 10. AD7703 Step Response

USING THE AD7703

SYSTEM DESIGN CONSIDERATIONS

The AD7703 operates differently from successive approximation

ADCs or integrating ADCs. Since it samples the signal continu-

ously, like a tracking ADC, there is no need for a start convert

command. The 20-bit output register is updated at a 4 kHz rate,

and the output can be read at any time, either synchronously or

asynchronously.

CLOCKING

The AD7703 requires a master clock input, which may be an exter-

nal TTL/CMOS compatible clock signal applied to the CLKIN

pin (CLKOUT not used). Alternatively, a crystal of the correct

frequency can be connected between CLKIN and CLKOUT,

when the clock circuit will function as a crystal controlled oscillator.

Figure 11 shows a simple model of the on-chip gate oscillator

and Table II gives some typical capacitor values to be used with

various resonators.

AD7703

⍀

10pF

= 1500

␮

MHO

SEE TABLE II

Figure 11. On-Chip Gate Oscillator

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

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