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AD7703AN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
REV. E
AD7703
–3–
Parameter A/S Version
2
B Version
2
C Version
2
Unit Test Conditions/Comments
POWER REQUIREMENTS
DC Power Supply Currents
8
Analog Positive Supply (AI
DD
) 2.7 2.7 2.7 mA max Typically 2 mA
Digital Positive Supply (DI
DD
)2 22mA max Typically 1 mA
Analog Negative Supply (AI
SS
) 2.7 2.7 2.7 mA max Typically 2 mA
Digital Negative Supply (DI
SS
) 0.1 0.1 0.1 mA max Typically 0.03 mA
Power Supply Rejection
9
Positive Supplies 70 70 70 dB typ
Negative Supplies 75 75 75 dB typ
Power Dissipation
Normal Operation 37 37 37 mW max SLEEP = Logic 1,
Typically 25 mW
Standby Operations
10
SLEEP = Logic 0,
A, B, C 20 20 20 µW max Typically 10 µW
S404040µW max
NOTES
1
The A
IN
pin presents a very high impedance dynamic load that varies with clock frequency. A ceramic 1 nF capacitor from the A
IN
pin to AGND is necessary.
Source resistance should be 750 or less.
2
Temperature ranges are as follows: A, B, C Versions: –40°C to +85° C; S Version: –55°C to +125°C.
3
Applies after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.
4
Total drift over the specified temperature range after calibration at power-up at 25°C. This is guaranteed by design and/or characterization. Recalibration at any
temperature will remove these errors.
5
In Unipolar mode, the offset can have a negative value (–V
REF
) such that the Unipolar mode can mimic Bipolar mode operation.
6
The specifications for input overrange and for input span apply additional constraints on the offset calibration range.
7
For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and negative full-scale
points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(V
REF
+ 0.1).
8
All digital outputs unloaded. All digital inputs at 5 V CMOS levels.
9
Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.
10
CLKIN is stopped. All digital inputs are grounded.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
DV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DV
DD
to AV
DD
. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DV
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AV
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DV
DD
+ 0.3 V
Analog Input Voltage to AGND . . . AV
SS
– 0.3 V to AV
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
2
. . . . . . . . ± 10 mA
Operating Temperature Range
Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C
Power Dissipation (DIP Package) to 75°C . . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
Power Dissipation (SOIC Package) to 75°C . . . . . . . 250 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . . 15 mW/°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Linearity
Temperature Error Package
Model Range (% FSR) Options*
AD7703AN –40°C to +85°C 0.003 N-20
AD7703BN –40°C to +85°C 0.0015 N-20
AD7703CN –40°C to +85°C 0.0012 N-20
AD7703AR –40°C to +85°C 0.003 R-20
AD7703BR –40°C to +85°C 0.0015 R-20
AD7703CR –40°C to +85°C 0.0012 R-20
AD7703AQ –40°C to +85°C 0.003 Q-20
AD7703BQ –40°C to +85°C 0.0015 Q-20
AD7703CQ –40°C to +85°C 0.0012 Q-20
AD7703SQ –55°C to +125°C 0.003 Q-20
*N = Plastic DIP; R = SOIC; Q = CERDIP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7703 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. E–4–
AD7703
Limit at T
MIN
, T
MAX
Limit at T
MIN
, T
MAX
Parameter (A, B Versions) (S, T Versions) Unit Conditions/Comments
f
CLKIN
3, 4
200 200 kHz min Master Clock Frequency: Internal Gate Oscillator
55MHz max Typically 4.096 MHz
200 200 kHz min Master Clock Frequency: Externally Supplied
55MHz max
t
r
5
50 50 ns max Digital Output Rise Time. Typically 20 ns.
t
f
5
50 50 ns max Digital Output Fall Time. Typically 20 ns.
t
1
00ns min SC1, SC2 to CAL High Setup Time
t
2
50 50 ns min SC1, SC2 Hold Time after CAL Goes High
t
3
6
1000 1000 ns min SLEEP High to CLKIN High Setup Time
SSC MODE
t
4
7
3/f
CLKIN
3/f
CLKIN
ns max Data Access Time (CS Low to Data Valid)
t
5
100 100 ns max SCLK Falling Edge to Data Valid Delay (25 ns typ)
t
6
250 250 ns min MSB Data Setup Time. Typically 380 ns.
7
300 300 ns max SCLK High Pulsewidth. Typically 240 ns.
t
8
790 790 ns max SCLK Low Pulsewidth. Typically 730 ns.
t
9
8
l/f
CLKIN
+ 200 l/f
CLKIN
+ 200 ns max SCLK Rising Edge to Hi-Z Delay (l/f
CLKIN
+ 100 ns typ)
t
10
8, 9
4/f
CLKIN
+ 200 4/f
CLKIN
+ 200 ns max CS High to Hi-Z Delay
SEC MODE
f
SCLK
55MHz max Serial Clock Input Frequency
t
11
35 35 ns min SCLK Input High Pulsewidth
t
12
160 160 ns min SCLK Low Pulsewidth
t
13
7, 10
160 160 ns max Data Access Time (CS Low to Data Valid). Typically 80 ns.
t
14
11
150 150 ns max SCLK Falling Edge to Data Valid Delay. Typically 75 ns.
t
15
8
250 250 ns max CS High to Hi-Z Delay
t
16
8
200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 1 to 6.
3
CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
4
The AD7703 is production tested with f
CLKIN
at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
5
Specified using 10% and 90% points on waveform of interest.
6
In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met.
7
t
4
and t
13
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
8
t
9
, t
10
, t
15
, and t
16
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is
the true bus relinquish time of the part and as such is independent of external bus loading capacitance.
9
If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
10
If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be
as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high
sooner than four CLKIN cycles plus 160 ns after CS goes low.
11
SDATA is clocked out on the falling edge of the SCLK input.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2
(AV
DD
= DV
DD
= +5 V ⴞ 10%; AV
SS
= DV
SS
= –5 V ⴞ 10%; AGND = DGND = O V;
f
CLKIN
= 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DV
DD
; unless otherwise noted.)
C
L
100pF
TO
OUTPUT
PIN
I
OH
200␮A
2.1V
+
I
OL
1.6mA
Figure 1. Load Circuit for Access Time
and Bus Relinquish Time
CAL
SC1, SC2
SC1, SC2 VALID
t
1
t
2
Figure 2. Calibration Control Timing
CLKIN
SLEEP
t
3
Figure 3. Sleep Mode Timing
REV. E
AD7703
–5–
DATA
VA LI D
t
15
HI-Z
SDATA
CS
Figure 5b. SEC Mode Data Hold Time
HI-Z
DB19
DB18
DB1 DB0
HI-Z
SCLK
SDATA
CLKIN
CS
HI-Z
t
7
t
8
t
5
t
9
t
4
t
8
HI-Z
Figure 6. SSC Mode Timing Diagram
DEFINITION OF TERMS
Linearity Error
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero-scale (not to be
confused with bipolar zero), a point 0.5 LSB below the first code
transition (000 . . . 000 to 000 . . . 001) and full-scale, a point
1.5 LSB above the last code transition (111 . . . 110 to 111 . . .
111). The error is expressed as a percentage of full scale.
Differential Linearity Error
This is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential linearity error is expressed in
LSB. A differential linearity specification of ± 1 LSB or less
guarantees monotonicity.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 111) from the ideal (V
REF
± 3/2 LSB).
It applies to both positive and negative analog input ranges and
is expressed in microvolts.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal (AGND + 0.5 LSB) when operating in the
Unipolar mode.
Bipolar Zero Error
This is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operating
in the Bipolar mode. It is expressed in microvolts.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal
(–V
REF
+ 0.5 LSB) when operating in the Bipolar mode.
Positive Full-Scale Overrange
Positive full-scale overrange is the amount of overhead available
to handle input voltages greater than +V
REF
(for example, noise
peaks or excess voltages due to system gain errors in system
calibration routines) without introducing errors due to overloading
the analog modulator or overflowing the digital filter.
Negative Full-Scale Overrange
This is the amount of overhead available to handle voltages below
–V
REF
without overloading the analog modulator or overflowing
the digital filter. Note that the analog input will accept negative
voltage peaks even in the Unipolar mode.
Offset Calibration Range
In the system calibration modes (SC2 low), the AD7703 calibrates
its offset with respect to the A
IN
pin. The offset calibration range
specification defines the range of voltages, expressed as a
percentage of V
REF
, that the AD7703 can accept and still accurately
calibrate offset.
Full-Scale Calibration Range
This is the range of voltages that the AD7703 can accept in the
system calibration mode and still correctly calibrate full scale.
Input Span
In system calibration schemes, two voltages applied in sequence
to the AD7703’s analog input define the analog input range. The
input span specification defines the minimum and maximum
input voltages from zero to full scale that the AD7703 can accept
and still accurately calibrate gain. The input span is expressed
as a percentage of V
REF.
DATA
VA LI D
t
10
HI-Z
SDATA
CS
Figure 4. SSC Mode Data Hold Time
HI-Z
DB18
DB1
DB0
HI-Z
SDATA
DRDY
CS
t
12
t
11
t
13
t
14
SCLK
t
16
DB19
Figure 5a. SEC Mode Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD7703AN

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Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 20-Bit IC
Lifecycle:
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