Table 15: DDR2 I
DD
Specifications and Conditions – 4GB
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 -53E -40E Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
I
DD0
1
1125 990 900 900 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL =
4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN
(I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as I
DD4W
I
DD1
1
1575 1395 1035 1035 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
I
DD2P
2
180 180 180 180 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
I
DD2Q
2
1170 990 810 720 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
I
DD2N
2
1260 1080 900 810 mA
Active power-down current: All device banks open;
t
CK
=
t
CK (I
DD
); CKE is LOW; Other control and address bus in-
puts are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
2
810 720 630 540 mA
Slow PDN exit
MR[12] = 1
252 252 252 252
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
I
DD3N
2
1170 990 810 720 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX
(I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
I
DD4W
1
1710 1440 1260 1215 mA
Operating burst read current: All device banks open; Continuous burst
read, I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS
MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
I
DD4R
1
1800 1620 1440 1350 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC
(I
DD
) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
I
DD5
2
5400 5040 4680 4500 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I
DD6
2
180 180 180 180 mA
512MB, 1GB, 2GB, 4GB (x72, DR) 240-Pin DDR2 SDRAM UDIMM
I
DD
Specifications
PDF: 09005aef80e8ad4d
htf18c64_128_256_512x72ay – Rev. I 3/10 EN
19
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