NCP81152
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7
Application Information
The NCP81152 is a high−performance dual MOSFET
gate driver optimized to drive the gates of both high−side
and low−side power MOSFETs in a synchronous buck
converter. Two drivers are co−packaged into a 2.5 mm x 3.5
mm QFN16 package that greatly reduces the footprint
compared to two discrete drivers.
Undervoltage Lockout
DRVH and DRVL are low until VCC reaches the VCC
UVLO threshold, typically 4.35 V. When VCC reaches this
threshold, the PWM signal controls the states of DRVH and
DRVL. There is a 200 mV hysteresis on VCC UVLO. There
are pull−down resistors on DRVH, DRVL and SW that
prevent the gates of the MOSFETs from accumulating
enough charge to turn on when the driver is powered off.
Three−State EN Signal
Placing EN into a logic−high or logic−low turns the driver
on and off, respectively, as long as VCC is greater than the
UVLO threshold. The EN threshold limits are specified in
the electrical characteristics table in this datasheet. Setting
the EN voltage to a mid−state level pulls both DRVH and
DRVL low.
Setting EN to the mid−state level can be used for body
diode braking to quickly reduce the inductor current. By
turning the LS FET off and having the current conduct
through the LS FET body diode, the voltage at the switch
node is at a greater negative potential compared to having
the LS FET on. This greater negative potential on switch
node allows there to be a greater voltage across the output
inductor, since the opposite terminal of the inductor is
connected to the converter output voltage. The larger
voltage across the inductor causes there to be a greater
inductor current slew rate, allowing the current to decrease
at a faster rate.
PWM Input and Zero Cross Detect (ZCD)
The PWM input, along with EN and ZCD, controls the
state of DRVH and DRVL. When PWM is set high, DRVH
is set high after the adaptive non−overlap delay. When PWM
is set low, DRVL is set high after the adaptive non−overlap
delay.
When PWM is set to the mid−state, DRVH is set low, and
after the adaptive non−overlap delay, DRVL is set high.
DRVL remains high until the ZCD blanking time expires.
When the timer expires, the voltage on the SW pin is
monitored for zero cross detection (whether it has crossed
the ZCD threshold voltage). After zero cross is detected,
DRVL is set low.
Low−Side Driver
The low−side driver is designed to drive a
ground−referenced low−R
DS(on)
N−channel MOSFET. The
voltage supply for the low−side driver is internally
connected to the VCC and GND pins.
High−Side Driver
The high−side driver is designed to drive a floating
low−R
DS(on)
N−channel MOSFET. The gate voltage for the
high−side driver is developed by a bootstrap circuit
referenced to the SW pin.
The bootstrap circuit is comprised of the integrated diode
and an external bootstrap capacitor. When the NCP81152 is
starting up, the SW pin is held at ground, allowing the
bootstrap capacitor to charge up to VCC through the
bootstrap diode. When the PWM input is driven high, the
high−side driver turns on the high−side MOSFET using the
stored charge of the bootstrap capacitor. As the high−side
MOSFET turns on, the SW pin rises. When the high−side
MOSFET fully turns on, SW settles to VIN and BST settles
to VIN + VCC (excluding parasitic ringing).
Bootstrap Circuit
The bootstrap circuit relies on an external charge storage
capacitor (C
BST
) and an integrated diode to provide current
to the high−side driver. A multi−layer ceramic capacitor
(MLCC) with a value greater than 100 nF should be used for
C
BST
.
Thermal Considerations
As power in the NCP81152 increases, it may be necessary
to provide thermal relief. The maximum power dissipation
supported by the device depends upon board design and
layout. Mounting pad configuration on the PCB, the board
material, and the ambient temperature affect the rate of
junction temperature rise for the part. When the NCP81152
has good thermal conductivity through the PCB, the
junction temperature is relatively low with high power
applications. The maximum dissipation the NCP81152 can
handle is given by:
P
D(MAX)
+
ƪ
T
J(MAX)
* T
A
ƫ
R
qJA
(eq. 1)
Since T
J
is not recommended to exceed 150°C, the
NCP81152, soldered on to a 645 mm
2
copper area, using
1 oz. copper and FR4, can dissipate up to 4.3 W when the
ambient temperature (T
A
) is 25°C. The power dissipated by
the NCP81152 can be calculated from the following
equation:
P
D
[ VCC @
ƪ
(n
HS
@ Qg
HS
) n
LS
@ Qg
LS
) @ f ) I
standby
ƫ
(eq. 2)
Where n
HS
and n
LS
are the number of high−side and
low−side FETs, respectively, Qg
HS
and Qg
LS
are the gate
charges of the high−side and low−side FETs, respectively
and f is the switching frequency of the converter.
