9FG430AFLFT Datasheet 9FG430AGILFT, 9FG430AGLF, 9FG430AGILF | P10-P12

IDT

Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17

9FG430

Four Output Differential Frequency Generator for PCIe Gen3 and QPI

Differential Clock Tolerances

x1 = 14.31818MHz

Clock Periods - Differential Outputs with Spread Spectrum Disabled

1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock

-c2c jitter

AbsPer

Min

-SSC

Short-Term

Average

Min

- ppm

Long-Term

Average

Min

0 ppm

Period

Nominal

+ ppm

Long-Term

Average

Max

+SSC

Short-

Term

Average

Max

+c2c

jitter

AbsPer

Max

35 100.00 9.94965 9.99965 10.00000 10.00035 10.05035 ns 1,2

-114 125.00 7.95091 8.00091 8.00000 7.99909 8.04909 ns 1,2

35 133.33 7.44974 7.49974 7.50000 7.50026 7.55026 ns 1,2

-104 166.67 5.95062 6.00062 6.00000 5.99937 6.04937 ns 1,2

35 200.00 4.94983 4.99983 5.00000 5.00018 5.05018 ns 1,2

42 266.67 3.69984 3.74984 3.75000 3.75016 3.80016 ns 1,2

-104 333.33 2.95031 3.00031 3.00000 2.99969 3.04969 ns 1,2

35 400.00 2.44991 2.49991 2.50000 2.50009 2.55009 ns 1,2

Clock Periods - Differential Outputs with Spread Spectrum Enabled

1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock

-c2c jitter

AbsPer

Min

-SSC

Short-Term

Average

Min

- ppm

Long-Term

Average

Min

0 ppm

Period

Nominal

+ ppm

Long-Term

Average

Max

+SSC

Short-

Term

Average

Max

+c2c

jitter

AbsPer

Max

199 99.75 9.94906 9.99906 10.02406 10.02506 10.02706 10.05206 10.10206 ns 1,2

-100 124.69 7.94925 7.99925 8.01925 8.02005 8.01925 8.03925 8.08925 ns 1,2

199 133.00 7.44930 7.49930 7.51805 7.51880 7.52029 7.53904 7.58904 ns 1,2

10 166.25 5.94943 5.99943 6.01443 6.01504 6.01510 6.03010 6.08010 ns 1,2

199 199.50 4.94953 4.99953 5.01203 5.01253 5.01353 5.02603 5.07603 ns 1,2

-140 266.00 3.69965 3.74965 3.75902 3.75940 3.75887 3.76825 3.81825 ns 1,2

10 332.50 2.94972 2.99972 3.00722 3.00752 3.00755 3.01505 3.06505 ns 1,2

199 399.00 2.44977 2.49977 2.50602 2.50627 2.50676 2.51301 2.56301 ns 1,2

Guaranteed by design and characterization, not 100% tested in production.

SSC ON

-0.5%

Down

Spread

Center

Freq.

MHz

Synthesis

Error

(ppm)

Measurement Windo

Units

Center

Freq.

MHz

Measurement Windo

Units

All ppm specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL frequency.

SSC OFF

or SSC +/-

0.25%

Center

Spread

Synthesis

Error

(ppm)

DIF

Notes

IDT

Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17

9FG430

Four Output Differential Frequency Generator for PCIe Gen3 and QPI

General SMBus serial interface information for the 9FG430

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address DC

(H)

• IDT clock will

acknowledge

• Controller (host) sends the begining byte location = N

• IDT clock will

acknowledge

• Controller (host) sends the data byte count = X

• IDT clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

(see Note 2)

• IDT clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address DC

(H)

• IDT clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• IDT clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address DD

(H)

• IDT clock will

acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends

Byte N + X -1

• IDT clock sends

Byte 0 through byte X (if X

(H)

was written to byte 8)

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

IDT (Slave/Receiver)

ACK

PstoP bit

X Byte

Index Block Write Operation

Slave Address DC

(H)

Beginning Byte = N

WRite

starT bit

Controller (Host)

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

T starT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

Slave Address DD

(H)

Index Block Read Operation

Slave Address DC

(H)

Beginning Byte = N

ACK

Data Byte Count = X

ACK

IDT (Slave/Receiver)

Controller (Host)

X Byte

ACK

IDT

Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17

9FG430

Four Output Differential Frequency Generator for PCIe Gen3 and QPI

SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)

Pin # Name Control Function Type 0 1 Default

Bit 7

RW Pin 17

Bit 6

RW Pin 6

Bit 5

RW Pin 24

Bit 4

RW Pin 25

Bit 3

RW Off On Pin 16

Bit 2

RW Hardware Select Software Select 0

Bit 1

RW Driven Hi-Z 0

Bit 0

RW Down Center 0

Notes:

1. These bits reflect the state of the corresponding pins at power up, but may be written to

if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.

SMBus Table: Output Enable Register

Pin # Name Control Function Type 0 1 Default

Bit 7

Bit 6

DIF_3 EN Output Enable RW Disable Enable 1

Bit 5

DIF_2 EN Output Enable RW Disable Enable 1

Bit 4

Bit 3

Bit 2

DIF_1 EN Output Enable RW Disable Enable 1

Bit 1

DIF_0 EN Output Enable RW Disable Enable 1

Bit 0

SMBus Table: Output Stop Control Register

Pin # Name Control Function Type 0 1 Default

Bit 7

Bit 6

DIF_3 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 5

DIF_2 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 4

Bit 3

Bit 2

DIF_1 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 1

DIF_0 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 0

Reserved

Byte 0

16 Spread Enable

Enable Software Control of Frequency, Spread Enable

(Spread Type always Software Control)

DIF_STOP# drive mode

SPREAD TYPE

Byte 1

Byte 2

See Frequency Selection Table,

Page 1

FS3

FS2

FS1

FS0

Reserved

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

9FG430AFLFT

Mfr. #:

Buy 9FG430AFLFT

Manufacturer:

IDT

Description:

Clock Generators & Support Products PCIE SYNTHESIZER - GEN3, 4 OUTPUT

Lifecycle:

New from this manufacturer.

Delivery:

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9FG430AFLFT

9FG430AFLFT

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