IDT
®
Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17
9FG430
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
15
SMBus Table: PLL Frequency Control Register
Pin # Name Control Function Type 0 1 Default
Bit 7
PLL N Div7 RW X
Bit 6
PLL N Div6 RW X
Bit 5
PLL N Div5 RW X
Bit 4
PLL N Div4 RW X
Bit 3
PLL N Div3 RW X
Bit 2
PLL N Div2 RW X
Bit 1
PLL N Div1 RW X
Bit 0
PLL N Div0 RW X
SMBus Table: PLL Spread Spectrum Control Register
Pin # Name Control Function Type 0 1 Default
Bit 7
PLL SSP7 RW X
Bit 6
PLL SSP6 RW X
Bit 5
PLL SSP5 RW X
Bit 4
PLL SSP4 RW X
Bit 3
PLL SSP3 RW X
Bit 2
PLL SSP2 RW X
Bit 1
PLL SSP1 RW X
Bit 0
PLL SSP0 RW X
SMBus Table: PLL Spread Spectrum Control Register
Pin # Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
PLL SSP14 RW X
Bit 5
PLL SSP13 RW X
Bit 4
PLL SSP12 RW X
Bit 3
PLL SSP11 RW X
Bit 2
PLL SSP10 RW X
Bit 1
PLL SSP9 RW X
Bit 0
PLL SSP8 RW X
-
Spread Spectrum
Programming bit(14:8)
These Spread Spectrum bits in
Byte 12 and 13 will program the
spread pecentage of PLL. The
user does not need to modify
these settings unless non-
standard spread amounts are
required. The part defaults to -
0.5% spread when spread is
enabled.
-
-
-
-
-
-
-
Byte 13
- Reserved
Byte 12
-
Spread Spectrum
Programming bit(7:0)
These Spread Spectrum bits in
Byte 12 and 13 will program the
spread pecentage of PLL. The
user does not need to modify
these settings unless non-
standard spread amounts are
required. The part defaults to -
0.5% spread when spread is
enabled.
-
-
-
-
-
-
The decimal representation of M
and N Divider in Byte 10 and 11 will
configure the PLL VCO frequency.
Default at power up = latch-in or
Byte 0 Rom table. VCO Frequency
= fXTAL x [NDiv(9:0)+8] /
[MDiv(5:0)+2]. The user does NOT
need to program these resgisters
for standard frequencies.
-
-
-
-
-
-
-
Byte 11
-
N Divider Programming
Byte11 bit(7:0) and Byte10
bit(7:6)
