IDT
®
Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17
9FG430
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
4
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
DD
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C
1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor
g
uaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%; See Test Loads s for loading conditions.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
T
COM
Commmercial range 0 70 °C 1
T
IND
Industrial range -40 85 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2V
DD
+ 0.3 V 1
Input Low Voltage V
IL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
GND
- 0.3 0.8 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
SEL14M_25M# = 0 25 MHz 1
SEL14M_25M# = 1 14.31818 MHz 1
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INXTAL
Crystal inputs 6 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1.8 ms 1,2
Input SS Modulation
Frequency
f
MODIN
Allowable Frequency
(Triangular Modulation)
30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 cycles 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 100 kHz 1,5
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swin
g
.
5
The differential in
p
ut clock must be runnin
g
for the SMBus to be active
Ambient Operating
Temperature
Input Current
3
Time from deassertion until out
uts are >200 mV
4
DIF_IN input
Capacitance
Input Frequency F
in
IDT
®
Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17
9FG430
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
5
Electrical Characteristics - Current Consumption
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DD3.3
VDD, All outputs active @100MHz
80 95
mA 1
I
DDA3.3OP
VDDA, All outputs active @100MHz
25 30
mA 1
I
DD3.3
VDD, All outputs active @400MHz
100 120
mA 1
I
DDA3.3OP
VDDA, All outputs active @400MHz
25 30
mA 1
I
DD3.3PD
VDD, All differential pairs driven 75 90 mA 1
I
DDA3.3PD
VDDA, All differential pairs driven 25 30 mA 1
I
DD3.3PD
Z
VDD, All differential pairs tri-stated 25 30 mA 1
I
DDA3.3PDZ
VDDA, All differential pairs tri-stated 25 30 mA 1
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
I
REF
= V
DD
/
(3xR
R
). For R
R
= 475
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
.
TA = TCOM or TIND; Supply Volta
g
e VDD = 3.3 V +/-5%, See Test Loads for loadin
g
Operating Supply Current
Powerdown Current
Electrical Characteristics - Output Duty Cycle, Jitter, and Skew Characterisitics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle t
D
C
Measured differentially, PLL Mode 45 55 % 1
Skew, Output to Output t
sk3
V
T
= 50% 50 ps 1
Jitter, Cycle to cycle t
j
c
y
c-c
y
c
25M input 50 ps 1,3
Jitter, Cycle to cycle t
jcyc-cyc
14.318M input 60 ps 1,3
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
I
REF
= V
DD
/
(3xR
R
). For R
R
= 475
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
.
3
Measured from differential waveform
4
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%; See Test Loads s for loading conditions.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Scope averaging on 1 4
V/ns
1, 2, 3
Slew rate matchin
g
Trf Slew rate matchin
g
, Scope avera
g
in
g
on 20
%
1, 2, 4
Voltage High VHigh 660 850 1
Voltage Low VLow -150 150 1
Max Voltage Vmax 1150 1
Min Volta
g
e Vmin -300 1
Vswin
g
Vswin
g
Scope avera
g
in
g
off 300 mV 1, 2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 550 mV 1, 5
Crossing Voltage (var)
-Vcross Scope averaging off 140 mV 1, 6
2
Measured from differential waveform
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Measurement on single ended signal using
absolute value. (Scope avera
g
in
g
off)
mV
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475
(1%), I
REF
= 2.32mA.
I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
(100
differential impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope uses for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
IDT
®
Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17
9FG430
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
6
Electrical Characteristics - Phase Jitter Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
t
jp
hPCIeG1
PCIe Gen 1 86 ps (p-p) 1,2,3,6
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
3
ps
(rms)
1,2,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
3.1
ps
(rms)
1,2,6
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
1
ps
(rms)
1,2,4,5,
6
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.5
ps
(rms)
1,5,6
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
0.3
ps
(rms)
1,5,6
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
0.2
ps
(rms)
1,5,6
1
Guaranteed by design and characterization, not 100% tested in production.
6
Applies to all differential outputs
Phase Jitter, QPI/SMI
2
See htt
p
://www.
p
cisi
g
.com for com
p
lete s
p
ecs
t
jphQPI_SMI
t
jphPCIeG2
Phase Jitter, PCI Express
3
Sam
p
le size of at least 100K c
y
cles. This fi
g
ures extra
p
olates to 108
p
s
p
k-
p
k @ 1M c
y
cles for a BER of 1-12.
4
Sub
j
ect to final radification b
y
PCI SIG.
5
Calculated from Intel-su
pp
lied Clock Jitter Tool v 1.6.3
Electrical Characteristics - REF-14.318/25 MHz
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values ppm 1
Clock period T
p
eriod
14.318MHz output nominal 69.8413 ns 1,2
Clock period T
p
eriod
25.000MHz output nominal 40 ns 1,2
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.4 V 1
Output High Current I
OH
V
OH
@MIN = 1.0 V, V
OH
@MAX = 3.135 V -29 -23 mA 1
Output Low Current I
OL
V
OL
@MIN = 1.95 V, V
OL
@MAX = 0.4 V 29 27 mA 1
Rise/Fall Time t
rf1
V
OL
= 0.4 V, V
OH
= 2.4 V 0.5 0.8 2 ns 1
Duty Cycle d
t1
V
T
= 1.5 V 45 55 % 1
Jitter t
jcyc-cyc
VT = 1.5 V 250 400 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
0
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818 or 25.00 MHz

9FG430AFLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products PCIE SYNTHESIZER - GEN3, 4 OUTPUT
Lifecycle:
New from this manufacturer.
Delivery:
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