CY22393
Automotive Three-PLL Serial-Programmable
Flash-Programmable Clock Generator
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-73555 Rev. *B Revised April 23, 2014
Automotive Three-PLL Serial-Programmable Flash-Programmable Clock Generator
Features
Three integrated phase-locked loops (PLLs)
Ultra-wide divide counters (8-bit Q, 11-bit P, and 7-bit post
divide)
Improved linear crystal load capacitors
Flash programmability with external programmer
Field-programmable
Low-jitter, high-accuracy outputs
Power management options (Shutdown, OE, Suspend)
Configurable crystal drive strength
Frequency select through three external LVTTL inputs
3.3-V operation
16-pin TSSOP package
CyClocksRT™ software support
AEC-Q100 Qualified
Available in A and E grade
Advanced Features
Two-wire serial interface for in-system configurability
Configurable output buffer
Digital VCXO
Functional Description
The CY22393 has three PLLs which, when combined with the
reference, allow up to four independent frequencies to be output
on up to six pins. These three PLLs are completely
programmable.
XTALIN
XTALOUT
S2/SUSPEND
SDAT
SCLK
SHUTDOWN
/OE
CONFIGURATION
FLASH
OSC.
XBUF
PLL1
CLKE
11-Bit P
8-Bit Q
PLL2
11-Bit P
8-Bit Q
PLL3
11-Bit P
8-Bit Q
4x4
Switch
Crosspoint
Divider
/2, /3, or /4
Divider
7-Bit
Divider
7-Bit
Divider
7-Bit
Divider
7-Bit
CLKA
CLKB
CLKC
CLKD
Logic Block Diagram – CY22393
CY22393
Document Number: 001-73555 Rev. *B Page 2 of 19
Contents
lPin Configuration............................................................. 3
Configurable PLLs....................................................... 3
General-Purpose Inputs .............................................. 4
Crystal Input ................................................................ 4
Crystal Drive Level and Power.................................... 4
Digital VCXO ............................................................... 4
Output Configuration ................................................... 4
Power-Saving Features............................................... 4
Improving Jitter............................................................ 5
Power Supply Sequencing .......................................... 5
CyClocksRT Software ...................................................... 5
Device Programming........................................................ 5
Junction Temperature Limitations ............................... 5
Dynamic Updates........................................................ 5
Memory Bitmap Definitions............................................. 5
Clk{A–D}_Div[6:0]........................................................ 5
ClkE_Div[1:0]............................................................... 5
Clk*_FS[2:0] ................................................................ 5
Xbuf_OE...................................................................... 6
PdnEn.......................................................................... 6
Clk*_ACAdj[1:0]........................................................... 6
Clk*_DCAdj[1:0] .......................................................... 6
PLL*_Q[7:0]................................................................. 6
PLL*_P[9:0] ................................................................. 6
PLL*_P0 ...................................................................... 6
PLL*_LF[2:0] ............................................................... 6
PLL*_En ...................................................................... 6
DivSel.......................................................................... 6
OscCap[5:0] ................................................................ 6
OscDrv[1:0] ................................................................. 6
Reserved..................................................................... 6
Serial Programming Bitmaps – Summary Tables ......... 7
Serial Bus Programming Protocol and Timing.............. 8
Default Startup Condition for the CY22393................. 8
Device Address ........................................................... 8
Data Valid.................................................................... 8
Data Frame ................................................................. 8
Acknowledge Pulse..................................................... 8
Write Operations............................................................... 8
Writing Individual Bytes............................................... 8
Writing Multiple Bytes.................................................. 8
Read Operations............................................................... 8
Current Address Read................................................. 8
Random Read ............................................................. 8
Sequential Read.......................................................... 8
Serial Programming Interface Timing........................... 10
Serial Programming Interface Timing Specifications . 10
Electrical Specifications................................................ 11
Absolute Maximum Conditions.................................. 11
Operating Conditions................................................. 11
Recommended Crystal Specifications....................... 11
3.3 V Electrical Characteristics.................................. 11
3.3 V Switching Characteristics................................. 12
Switching Waveforms.................................................... 13
Test Circuit...................................................................... 14
Ordering Information...................................................... 15
Possible Configurations............................................. 15
Package Diagram............................................................ 16
Acronyms........................................................................ 17
Document Conventions................................................. 17
Units of Measure....................................................... 17
Document History Page................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support....................... 19
Products.................................................................... 19
PSoC Solutions......................................................... 19
CY22393
Document Number: 001-73555 Rev. *B Page 3 of 19
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL1 is sent to the
cross point switch. The output of PLL1 is also sent to a /2, /3, or
/4 synchronous post-divider that is output through CLKE. The
frequency of PLL1 can be changed using serial programming or
by external CMOS inputs, S0, S1, and S2. See General-Purpose
Inputs on page 4 for more detail.
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL2 is sent to the
cross point switch. The frequency of PLL2 is changed using
serial programming.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL3 is sent to the
cross point switch. The frequency of PLL3 is changed using
serial programming.
Pin Configuration
Figure 1. Pin Diagram - 16-Pin TSSOP CY22393
Pin Definitions
Name Pin Number Description
CLKC 1 Configurable clock output C
V
DD
2 Power supply
AGND 3 Analog ground
XTALIN 4 Reference crystal input or external reference clock input
XTALOUT 5 Reference crystal feedback
XBUF 6 Buffered reference clock output
CLKD 7 Configurable clock output D
CLKE 8 Configurable clock output E
CLKB 9 Configurable clock output B
CLKA 10 Configurable clock output A
GND 11 Ground
SDAT (S0) 12 Serial port data. S0 value latched during start-up
SCLK (S1) 13 Serial port clock. S1 value latched during start-up
AV
DD
14 Analog power supply
S2/
SUSPEND
15 General-purpose input for frequency control; bit 2. Optionally, Suspend mode control input
SHUTDOWN
/
OE
16 Places outputs in tristate condition and shuts down chip when LOW. Optionally, only places outputs
in tristate condition and does not shut down chip when LOW

CY22393FXET

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Clock Generators & Support Products Programmable Clock
Lifecycle:
New from this manufacturer.
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