CY22393FXET Datasheet CY22393FXE, CY22393FXET, CY22393FXA | P4-P6

CY22393

Document Number: 001-73555 Rev. *B Page 4 of 19

General-Purpose Inputs

S2 is a general-purpose input that is programmed to enable two

frequency settings. The options that switch with this

general-purpose input are as follows: the frequency of PLL1, the

output divider of CLKB, and the output divider of CLKA.

The two frequency settings are contained within an eight-row

frequency table. The values of SCLK (S1) and SDAT (S0) pins

are latched during start-up and used as the other two indices into

this array.

CLKA and CLKB have seven-bit dividers that point to one of the

two programmable settings (register 0 or register 1). Both clocks

share a single register control and both must be set to register 0,

or both must be set to register 1.

For example, the part may be programmed to use S0, S1, and

S2 (0, 0, 0 to 1, 1, 1) to control eight different values of P and Q

on PLL1. For each PLL1 P and Q setting, one of the two CLKA

and CLKB divider registers can be chosen. Any divider change

as a result of switching S0, S1, or S2 is guaranteed to be

glitch-free.

Crystal Input

The input crystal oscillator is an important feature of CY24293

because of its flexibility and performance features.

The oscillator inverter has programmable drive strength. This

enables maximum compatibility with crystals from various

manufacturers. Parallel resonant, fundamental mode crystals

should be used.

The input load capacitors are placed on-die to reduce external

component cost. These capacitors are true parallel-plate

capacitors for ultra-linear performance. These were chosen to

reduce the frequency shift that occurs when nonlinear load

capacitance interacts with load, bias, supply, and temperature

changes. Nonlinear (FET gate) crystal load capacitors must not

be used for MPEG, communications, or other applications that

are sensitive to absolute frequency requirements.

The value of the load capacitors is determined by six bits in a

programmable register. The load capacitance can be set with a

resolution of 0.375 pF for a total crystal load range of 6 pF to

30 pF. Typical crystals have a C

specification in the range of

12 pF to 18 pF.

For driven clock inputs, the input load capacitors can be

bypassed. This allows the clock chip to accept driven frequency

inputs up to 166 MHz. If the application requires a driven input,

leave XTALOUT floating.

Crystal Drive Level and Power

Crystals are specified to accept a maximum drive level.

Generally, larger crystals can accept more power. For a specific

voltage swing, power dissipation in the crystal is proportional to

ESR and proportional to the square of the crystal frequency.

(Note that the actual ESR is sometimes much less than the value

specified by the crystal manufacturer.) Power is also almost

proportional to the square of C

Power can be reduced to less than the DL specified in Recom-

mended Crystal Specifications on page 11 by selecting a

reduced frequency crystal with low C

and low R

(ESR).

Digital VCXO

The serial programming interface is used to dynamically change

the capacitor load value on the crystal. A change in crystal load

capacitance corresponds with a change in the reference

frequency.

For special pullable crystals specified by Cypress, the

capacitance pull range is +150 ppm to –150 ppm from midrange.

Be aware that adjusting the frequency of the reference affects all

frequencies on all PLLs in a similar manner because all

frequencies are derived from the single reference.

Output Configuration

Under normal operation there are four internal frequency

sources that are routed through a programmable cross point

switch to any of the four programmable 7-bit output dividers. The

four sources are: reference, PLL1, PLL2, and PLL3. The

following is a description of each output.

■ CLKA’s output originates from the cross point switch and goes

through a programmable 7-bit post divider. The 7-bit post

divider derives its value from one of the two programmable

registers. See the section General-Purpose Inputs for more

information.

■ CLKB’s output originates from the cross point switch and goes

through a programmable 7-bit post divider. The 7-bit post

divider derives its value from one of the two programmable

registers. See the section General-Purpose Inputs for more

information.

■ CLKC’s output originates from the cross point switch and goes

through a programmable 7-bit post divider. The 7-bit post

divider derives its value from one programmable register.

■ CLKD’s output originates from the cross point switch and goes

through a programmable 7-bit post divider. The 7-bit post

divider derives its value from one programmable register.

■ CLKE’s output originates from PLL1 and goes through a post

divider that may be programmed to /2, /3, or /4.

■ XBUF is the buffered reference.

The clock outputs are designed to drive a single-point load with

a total lumped load capacitance of 15 pF. While driving multiple

loads is possible with the proper termination, it is generally not

recommended.

Power-Saving Features

The SHUTDOWN/OE input tristates the outputs when pulled

LOW. If system shutdown is enabled, a LOW on this pin also

shuts off the PLLs, counters, reference oscillator, and all other

active components. The resulting current on the V

pins is less

than 5 mA (typical). Relock the PLLs after leaving the shutdown

mode.

The S2/SUSPEND

input is configured to shut down a

customizable set of outputs and/or PLLs, when LOW. All PLLs

and any of the outputs are shut off in nearly any combination.

The only limitation is that if a PLL is shut off, all outputs derived

from it must also be shut off. Suspending a PLL shuts off all

associated logic, while suspending an output simply forces a

tristate condition.

CY22393

Document Number: 001-73555 Rev. *B Page 5 of 19

With the serial interface, each PLL and/or output is individually

disabled. This provides total control over the power savings.

Improving Jitter

Jitter Optimization Control is useful for mitigating problems

related to similar clocks switching at the same moment, causing

excess jitter. If one PLL is driving more than one output, the

negative phase of the PLL can be selected for one of the outputs

(CLKA–CLKD). This prevents the output edges from aligning and

allows superior jitter performance.

Power Supply Sequencing

There are no power supply sequencing requirements. The part

is not fully operational until all V

pins are brought up to the

voltages specified in the Operating Conditions on page 11.

All grounds must be connected to the same ground plane.

CyClocksRT Software

CyClocksRT is our second-generation software application that

allows users to configure this device. The easy-to-use interface

offers complete control of the many features of this device

including, but not limited to, input frequency, PLL and output

frequencies, and different functional options. It checks the data

sheet frequency range limitations and automatically applies

performance tuning. CyClocksRT also has a power estimation

feature that allows you to see the power consumption of a

specific configuration. You can download a free copy of

CyberClocks that includes CyClocksRT on Cypress’s web site,

www.cypress.com.

CyClocksRT is used to generate P, Q, and divider values used

in serial programming. There are many internal frequency rules

that are not documented in this datasheet, but are required for

proper operation of the device. Check these rules by using the

latest version of CyClocksRT.

Device Programming

Part numbers starting with CY22392F are ‘field programmable’

devices. Field programmable devices are shipped

unprogrammed and must be programmed prior to installation on

a PCB. After a programming file (.jed) is created using the

CyberClocks software, devices can be programmed in small

quantities using the CY3672 programmer and CY3698

[1]

adapter. Programming of the clock device should be done at

temperatures < 75 °C. Volume programming is available through

Cypress Semiconductor’s value-added distribution partners or

by using third-party programmers from BP Microsystems, HiLo

Systems, and others. For sufficiently large volumes, Cypress can

supply pre-programmed devices with a part number extension

that is configuration-specific.

Junction Temperature Limitations

It is possible to program this family such that the maximum

junction temperature rating is exceeded. The package θ

115 °C/W. Use the CyClocksRT power estimation feature to

verify that the programmed configuration meets the junction

temperature and package power dissipation maximum ratings.

Dynamic Updates

The output divider registers are not synchronized with the output

clocks. Changing the divider value of an active output is likely

cause a glitch on that output.

PLL P and Q data is spread between three bytes. Each byte

becomes active on the acknowledge for that byte, so changing

P and Q data for an active PLL can cause the PLL to try to lock

an out-of-bounds condition. Therefore, you must turn off the PLL

being programmed during the update. Do this by setting the

PLL*_En bit LOW.

PLL1, CLKA, and CLKB each have multiple registers supplying

data. To program these resources safely, always program an

inactive register, and then transition to that register. This allows

these resources to stay active during programming.

The serial interface is active even with the SHUTDOWN

/OE pin

LOW as the serial interface logic uses static components and is

completely self-timed. The part does not meet the I

DDS

current

limit with transitioning inputs.

Memory Bitmap Definitions

Clk{A–D}_Div[6:0]

Each of the four main output clocks (CLKA–CLKD) features a

7-bit linear output divider. Any divider setting between 1 and 127

may be used by programming the value of the desired divider

into this register. Odd divide values are automatically duty-cycle

corrected. Setting a divide value of zero powers down the divider

and forces the output to a tristate condition.

CLKA and CLKB have two divider registers, selected by the

DivSel bit (which, in turn, is selected by S2, S1, and S0). This

allows the output divider value to change dynamically.

ClkE_Div[1:0]

CLKE has a simpler divider (see Table 1).

Clk*_FS[2:0]

Each of the four main output clocks (CLKA–CLKD) has a

three-bit code that determines the clock sources for the output

divider. The available clock sources are: Reference, PLL1, PLL2,

and PLL3. Each PLL provides both positive and negative phased

outputs, for a total of seven clock sources (see Table 2). Note

that the phase is a relative measure of the PLL output phases.

No absolute phase relation exists at the outputs.

Note

1. CY3698 only supports programming of only the 16-pin TSSOP package.

Table 1. ClkE Divider

ClkE_Div[1:0] ClkE Output

00 Off

01 PLL1 0 ° Phase/4

10 PLL1 0 ° Phase/2

11 PLL1 0 ° Phase/3

CY22393

Document Number: 001-73555 Rev. *B Page 6 of 19

Xbuf_OE

This bit enables the XBUF output when HIGH.

PdnEn

This bit selects the function of the SHUTDOWN/OE pin. When

this bit is HIGH, the pin is an active LOW shutdown control. When

this bit is LOW, this pin is an active HIGH output enable control.

Clk*_ACAdj[1:0]

These bits modify the output predrivers, changing the duty cycle

through the pads. These are nominally set to 01, with a higher

value shifting the duty cycle higher. The performance of the

nominal setting is guaranteed.

Clk*_DCAdj[1:0]

These bits modify the DC drive of the outputs. The performance

of the nominal setting is guaranteed.

PLL*_Q[7:0]

PLL*_P[9:0]

PLL*_P0

These are the 8-bit Q value and 11-bit P values that determine

the PLL frequency. The formula is:

PLL*_LF[2:0]

These bits adjust the loop filter to optimize the stability of the PLL.

Table 4 can be used to guarantee stability. However,

CyClocksRT uses a more complicated algorithm to set the loop

filter for enhanced jitter performance. Use the Print Preview

function in CyClocksRT to determine the charge pump settings

for optimal jitter performance.

PLL*_En

This bit enables the PLL when HIGH. If PLL2 or PLL3 are not

enabled, then any output selecting the disabled PLL must have

a divider setting of zero (off). Because the PLL1_En bit is

dynamic, internal logic automatically turns off dependent outputs

when PLL1_En goes LOW.

DivSel

This bit controls which register is used for the CLKA and CLKB

dividers.

OscCap[5:0]

This controls the internal capacitive load of the oscillator. The

approximate effective crystal load capacitance is:

Set to zero for external reference clock.

OscDrv[1:0]

These bits control the crystal oscillator gain setting. These must

always be set according to Table 5. The parameters are the

Crystal Frequency, Internal Crystal Parasitic Resistance

(equivalent series resistance), and the OscCap setting during

crystal start-up, which occurs when power is applied, or after

shutdown is released. If in doubt, use the next higher setting.

For external reference, the use Table 6.

Reserved

These bits must be programmed LOW for proper operation of the

device.

Table 2. Clock Source

Clk*_FS[2:0] Clock Source

000 Reference Clock

001 Reserved

010 PLL1 0 ° Phase

011 PLL1 180 ° Phase

100 PLL2 0 ° Phase

101 PLL2 180 ° Phase

110 PLL3 0 ° Phase

111 PLL3 180 ° Phase

Table 3. Output Drive Strength

Clk*_DCAdj[1:0] Output Drive Strength

00 –30% of nominal

01 Nominal

10 +15% of nominal

11 +50% of nominal

PLL

REF

-------

⎝⎠

⎛⎞

×=

2P3+()×()PO+=

Q2+=

Equation 1

Table 4. Loop Filter Settings

PLL*_LF[2:0] P

Min P

Max

00016231

001 232 626

010 627 834

011 835 1043

100 1044 1600

Table 5. Crystal Oscillator Gain Settings

OscCap 00H–20H 20H–30H 30H–40H

Crystal Freq\ R 30 Ω 60 Ω 30 Ω 60 Ω 30 Ω 60 Ω

8–15 MHz 00 01 01 10 01 10

15–20 MHz 01 10 01 10 10 10

20–25 MHz 01 10 10 10 10 11

25–30 MHz 10 10 10 11 11 NA

Table 6. Osc Drv for External Reference

External Freq (MHz) 1–25 25–50 50–90 90–166

OscDrv[1:0] 00 01 10 11

LOAD

6pF OscCap 0.375pF×()+=

Equation 2

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

CY22393FXET

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CY22393FXET

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