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CY22393FXET

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CY22393
Document Number: 001-73555 Rev. *B Page 10 of 19
Serial Programming Interface Timing
Figure 5. Start and Stop Frame
Figure 6. Frame Format (Device Address, R/W
, Register Address, Register Data)
SDAT
SCLK
START
Transition
to next Bit
STOP
SDAT
SCLK
DA6 DA5 DA0 R/W ACK RA7 RA6 RA1 RA0 ACK STOP
START
ACK
D7 D6 D1 D0
+++
+
+
+
Serial Programming Interface Timing Specifications
Parameter Description Min Max Unit
f
SCLK
Frequency of SCLK – 400 kHz
Start mode time from SDA LOW to SCL LOW 0.6 – μs
CLK
LOW
SCLK LOW period 1.3 – μs
CLK
HIGH
SCLK HIGH period 0.6 – μs
t
SU
Data transition to SCLK HIGH 100 – ns
t
DH
Data hold (SCLK LOW to data transition) 100 – ns
Rise time of SCLK and SDAT – 300 ns
Fall time of SCLK and SDAT – 300 ns
Stop mode time from SCLK HIGH to SDAT HIGH 0.6 – μs
Stop mode to Start mode 1.3 – μs
CY22393
Document Number: 001-73555 Rev. *B Page 11 of 19
Electrical Specifications
Absolute Maximum Conditions
Supply voltage .............................................–0.5 V to +7.0 V
DC input voltage ......................... –0.5 V to + (AV
DD
+ 0.5 V)
Storage temperature ................................ –65 °C to +125 °C
Junction temperature
A Grade................................................................. 125 °C
E Grade.................................................................150 °C
Data retention at T
J
= 125 °C ...............................> 10 years
Data retention at T
J
= 150 °C .................................> 2 years
Maximum programming cycles ........................................100
Package power dissipation (A-Grade) .....................350 mW
Package power dissipation (E-Grade) .....................217 mW
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... >
2000 V
Latch-up (per JEDEC 17) ................................... >
±200 mA
Stresses exceeding absolute maximum conditions may cause
permanent damage to the device. These conditions are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated in the operation
sections of this datasheet is not implied. Extended exposure to
absolute maximum conditions may affect reliability.
Notes
2. External input reference clock must have a duty cycle between 40% and 60%, measured at V
DD
/2.
3. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
4. Guaranteed by design, not 100% tested.
5. Profile configuration through CyberClocks (JEDEC file) should be so generated such that Drive strength should be at ‘Mid Low’ or above.
Operating Conditions
Parameter Description Min Typ Max Unit
V
DD
/AV
DD
Supply voltage 3.135 3.3 3.465 V
T
A
Automotive A-Grade operating temperature, Ambient –40 – 85 °C
T
A
Automotive E-Grade operating temperature, Ambient -40 125 °C
C
LOAD_OUT
Maximum load capacitance – – 15 pF
f
REF
External reference crystal 8 – 30 MHz
External reference clock
[2]
, Automotive 1 – 150 MHz
Recommended Crystal Specifications
Parameter Description Description Min Typ Max Unit
F
NOM
Nominal crystal frequency Parallel resonance, fundamental mode 8 – 30 MHz
C
LNOM
Nominal load capacitance 8 – 20 pF
R
1
Equivalent series resistance (ESR) Fundamental mode – – 50 Ω
DL Crystal drive level No external series resistor assumed – 0.5 2 mW
3.3 V Electrical Characteristics
Parameter Description Conditions
[3]
Min Typ Max Unit
I
OH
Output high current
[4, 5]
V
OH
= V
DD
– 0.5 V, V
DD
= 3.3 V 12 24 – mA
I
OL
Output low current
[4, 5]
V
OL
= 0.5 V, V
DD
= 3.3 V 12 24 – mA
C
XTAL_MIN
Crystal load capacitance
[4]
Capload at minimum setting – 6 – pF
C
XTAL_MAX
Crystal load capacitance
[3]
Capload at maximum setting – 30 – pF
C
IN
Input pin capacitance
[4]
Except crystal pins – 7 – pF
V
IH
High-level input voltage CMOS levels,% of AV
DD
70% – – AV
DD
V
IL
Low-level input voltage CMOS levels,% of AV
DD
– 30% AV
DD
I
IH
Input high current V
IN
= AV
DD
– 0.3 V – <1 10 μA
I
IL
Input low current V
IN
= +0.3 V – <1 10 μA
I
OZ
Output leakage current Three-state outputs (OE = Low) – 10 μA
CY22393
Document Number: 001-73555 Rev. *B Page 12 of 19
I
DD
Total power supply current 3.3-V power supply; 2 outputs at 20 MHz;
4 outputs at 40 MHz
[6,7]
–50–mA
3.3-V power supply; 2 outputs at 166 MHz;
4 outputs at 83 MHz
[6,7]
–100–mA
I
DDS
Total power supply current in shutdown mode Shutdown active – 5 20 μA
3.3 V Electrical Characteristics (continued)
Parameter Description Conditions
[3]
Min Typ Max Unit
3.3 V Switching Characteristics
Parameter Description Conditions Min Typ Max Unit
1/t
1
Output frequency
[8, 9]
Clock output limit, CMOS, Automotive – – 166 MHz
t
2
Output duty cycle
[8, 10]
Duty cycle for outputs, defined as t
2
÷ t
1
,
Fout < 100 MHz, divider >
2, measured at
V
DD
/2
45% 50% 55%
Duty cycle for outputs, defined as t
2
÷ t
1
,
Fout > 100 MHz or divider = 1, measured at
V
DD
/2
40% 50% 60%
t
3
Rising edge slew rate
[8]
Output clock rise time, 20% to 80% of V
DD
0.75 1.4 – V/ns
t
4
Falling edge slew rate
[8]
Output clock fall time, 20% to 80% of V
DD
0.75 1.4 – V/ns
t
5
Output three-state timing
[8]
Time for output to enter or leave three-state
mode after SHUTDOWN
/OE switches
– 150 300 ns
t
6
Clock jitter
[8, 9]
Peak-to-peak period jitter, CLK outputs
measured at V
DD
/2
– 400 – ps
t
7
Lock time
[8]
PLL lock time from power-up – 1.0 3 ms
Notes
6. Profile configuration through CyberClocks (JEDEC file) should be so generated such that for E-Grade, I
DD
max < 56 mA (considering T
A
max = 125 °C).
7. Profile configuration through CyberClocks (JEDEC file) should be so generated such that for A - Grade, I
DD
max < 90 mA (considering T
A
max = 85 °C).
8. Guaranteed to meet 20%–80% output thresholds, duty cycle, and crossing point specifications.
9. Reference output duty cycle depends on XTALIN duty cycle.
10. Jitter varies significantly with configuration. Reference output jitter depends on XTALIN jitter and edge rate.
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CY22393FXET

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Manufacturer:
Cypress Semiconductor
Description:
Clock Generators & Support Products Programmable Clock
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