WM8788 Preliminary Technical Data
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PTD, December 2011, Rev 2.3
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DEVICE DESCRIPTION
INTRODUCTION
The WM8788 is a high-performance 24-bit stereo ADC designed for LCD televisions, DVD, Blu-Ray
and set-top box applications. It is packaged in a 16-pin TSSOP.
The device comprises two analogue input channels. External resistors are used to configure the
device for line level inputs at 1Vrms or for higher input signal levels.
The stereo hi-fi ADCs operate at sample rates from 8kHz to 192kHz. A high pass filter is provided in
the ADC path for removing DC offsets and suppressing low frequency noise.
The digital audio interface can operate in Master or Slave mode and supports the ADC output in
Right-justified, Left-justified or I2S format. The data word size is selectable between 16, 20 or 24 bits.
The device configuration is selected using hardware control inputs. The digital control inputs use tri-
state logic in order to support many different configuration selections.
The WM8788 incorporates an internal voltage reference and LDO regulator for power-efficient
operation from a single power supply. External clocking is required via the MCLK pin.
A power on reset (PoR) circuit ensures correct start-up and shut-down. The WM8788 is held in reset
when MCLK is not present, offering a low-power standby state.
CALIBRATED START-UP
SLAVE MODE
The WM8788 chip has a phase calibration circuit that is active in slave mode. This circuit
detects incoming clock phase relationship and configures the device automatically to ensure
best performance of the device.
Phase calibration starts as soon as the device comes out of reset, and takes 64 BCLK
periods from Power on Reset to complete. Note that once the clock signals are calibrated and
in phase, no further calibration will take place until the device next comes out of reset.
For the phase calibration to work effectively, the calibration must take place when the MCLK
and the BCLK signals are stable with a fixed phase relationship and running at the frequency
which the device will eventually operate. There are three different sequences that allow the
system designer to ensure that this can happen:
1. Ensure that MCLK and BCLK have a fixed phase relationship before LRCLK is
applied
2. After power-up, pause LRCLK for a minimum of 1 period
3. After power-up, stop MCLK for a minimum of 20 periods. Then re-start MCLK in a
fixed phase and frequency relationship to BCLK
In option (1), the device will be held in reset if no LRCLK is applied. MCLK and BLCK must be
in a fixed and final operation phase relationship and frequency before LRCLK is applied.
Options (2) and (3) both digitally reset the device, and can be used if the clock relationship
changes during operation to allow re-calibration to the new relationship.
If sample rate is changed, it is recommended that either Option 2 or Option 3 above is carried
out once the sample rate change is complete.
After the calibrated start-up sequence has completed, the phase relationship between MCLK
and BCLK must remain static to within 0.6ns. If there is a movement in the MCLK/BCLK
phase relationship of 0.6ns or over, performance degradation in SNR and THD+N of up to
6dB from the figures stated in the electrical characteristics can occur.
Note that phase calibration only takes place in Slave Mode. In Master Mode, the phase
calibration circuit is not required and is disabled.
MASTER MODE
In Master Mode operation, the device requires a reset operation after power-up to guarantee
SNR performance meets the performance stated in the electrical characteristics. To reset the
device after power-up, stop MCLK for a minimum of 20 periods then re-start MCLK.
