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WM8788GEDT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
Preliminary Technical Data WM8788
w
PTD, December 2011, Rev 2.3
13
DIGITAL AUDIO INTERFACE CONTROL
The digital audio interface protocol is selected using the control pins AIFMODE0 and AIFMODE1, as
described in Table 1.
AIFMODE1 AIFMODE0 FORMAT
0 0 16-bit Right-justified
0 1 20-bit Right-justified
0 Z 24-bit Right-justified
1 0 16-bit Left-justified
1 1 20-bit Left-justified
1 Z 24-bit Left-justified
Z 0 16-bit I2S
Z 1 20-bit I2S
Z Z 24-bit I2S
Table 1 Digital Audio Interface Mode Select
For Slave Mode, set MASTER = 0 and set OSR according to the applicable sample rate.
MASTER OSR SAMPLE RATE
0 0 8, 16, 32, 44.1, 48kHz
0 1 88.2, 96kHz
0 Z 176.4, 192kHz
Table 2 Slave Mode Configuration
In Slave Mode, the MCLK and LRCLK inputs must conform to a valid clocking ratio, as noted below.
The LRCLK frequency is the same as the sample rate, fs. MCLK frequencies of 128fs, 192fs, 256fs,
384fs, 512fs and 768fs can be supported, depending on the sample rate.
The BCLK signal is an input to the WM8788 in slave mode. A range of BCLK frequencies can be
supported, provided there are sufficient BCLK cycles for the selected data word length. The BCLK
frequency must not be higher than the MCLK frequency, and must not be higher than 12.288MHz.
SAMPLE RATE MCLK FREQUENCY (MHz)
128fs 192fs 256fs 384fs 512fs 768fs
8kHz n/a n/a 2.048 3.072 4.096 6.144
16kHz n/a n/a 4.096 6.144 8.192 12.288
32kHz n/a n/a 8.192 12.288 16.384 24.576
44.1kHz n/a n/a 11.2896 16.9344 22.5792 33.8688
48kHz n/a n/a 12.288 18.432 24.576 36.864
88.2kHz 11.2896 16.9344 22.5792 33.8688 n/a n/a
96kHz 12.288 18.432 24.576 36.864 n/a n/a
176.4kHz 22.5792 33.8688 n/a n/a n/a n/a
192kHz 24.576 36.864 n/a n/a n/a n/a
Table 3 MCLK Frequency in Slave Mode
WM8788 Preliminary Technical Data
w
PTD, December 2011, Rev 2.3
14
For Master Mode, set MASTER and OSR according to the applicable sample rate and clocking ratio.
MASTER OSR CLOCKING RATIO SAMPLE RATE
1 0 384fs 8, 16, 32, 44.1, 48kHz
1 1 384fs 88.2, 96kHz
Z 0 256fs 8, 16, 32, 44.1, 48kHz
Z 1 256fs 88.2, 96kHz
Table 4 Master Mode Configuration
In Master Mode, the sample rate (fs) is determined by the MCLK frequency and by the selected
clocking ratio. The LRCLK frequency is the same as the sample rate, and is output by the WM8788 in
master mode.
The BCLK signal is output by the WM8788 in master mode. The BCLK frequency is LRCLK x 64.
MASTER AND SLAVE MODE OPERATION
The digital audio interface can be configured as a Master or a Slave interface, depending on the state
of the MASTER control pin described earlier. The two modes are illustrated in Figure 6 and Figure 7.
WM8788
ADCDAT
LRCLK
BCLK
Processor WM8788
ADCDAT
LRCLK
BCLK
Processor
Figure 6 Master Mode Figure 7 Slave Mode
In Master mode, LRCLK and BCLK are configured as outputs, and the WM8788 controls the timing of
the data transfer on the ADCDAT pin.
In Master mode, the LRCLK frequency is determined automatically according to the MCLK frequency
and the selected clocking ratio. The BCLK frequency is LRCLK x 64.
In Slave mode, LRCLK and BCLK are configured as inputs, and the data timing is controlled by an
external master.
AUDIO DATA FORMATS
Three audio data formats are supported by the digital audio interface:
Right-justified
Left-justified
I
2
S
All of these modes are MSB first, and are illustrated below. Refer to the “Signal Timing Requirements”
section for timing information.
Preliminary Technical Data WM8788
w
PTD, December 2011, Rev 2.3
15
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 8 Right Justified Audio Interface (assuming n-bit word length)
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 9 Left Justified Audio Interface (assuming n-bit word length)
In I
2
S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 10 I
2
S Justified Audio Interface (assuming n-bit word length)
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WM8788GEDT

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Manufacturer:
Cirrus Logic
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Audio A/D Converter ICs STEREO ADC
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