8432I-101 Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 8, 20162
set the M divider and N output divider to a specifi c default state
that will automatically occur during power-up. The TEST output is
LOW when operating in the parallel input mode. The relationship
between the VCO frequency, the input frequency and the M divider
is defi ned as follows:
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 25MHz reference
are defi ned as 8 ≤ M ≤ 28. The frequency out is defi ned as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N out-
put divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output divider on each rising
edge of S_CLOCK. The serial mode can be used to program the
M and N bits and test bits T1 and T0. The internal registers T0
and T1 determine the state of the TEST output as follows:
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation
using a 25MHz clock input. Valid PLL loop divider values for different
input frequencies are defi ned in the Input Frequency Characteristics,
Table 5, NOTE 1.
The 8432I-101 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A differential clock input is used as the input to the 8432I-
101. This input is fed into the phase detector. A 25MHz clock input
provides a 25MHz phase detector reference frequency. The VCO of
the PLL operates over a range of 250MHz to 700MHz. The output
of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjust-
ing the VCO control voltage. Note, that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent
to each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the 8432I-101 support two
input modes to program the PLL M divider and N output divider.
The two input operational modes are parallel and serial. Figure1
shows the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 and N0 and N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a serial
event occurs. As a result, the M and N bits can be hardwired to
fVCO = f
IN
x M
T1 T0 TEST Output
0 0 LOW
0 1 S_Data, Shift Register Input
1 0 Output of M divider
1 1 CMOS Fout
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
fOUT = fVCO = f
IN
x M
N
N
