8432I-101 Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 8, 20168
STORAGE AREA NETWORKS
A variety of technologies are used for interconnection of the
elements within a SAN. The tables below list the common application
Table 7. Common SANs Application Frequencies
Table 8. Confi guration Details for SANs Applications
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 8432I-101 pro-
vides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and
V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V
CCA
pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 2. POWER SUPPLY FILTERING
10Ω
V
CCA
10 μF
.01μF
3.3V
.01μF
V
CC
Interconnect Technology Clock Rate
Reference Frequency to SERDES
(MHz)
Crystal Frequency
(MHz)
Gigabit Ethernet 1.25 GHz 125, 250, 156.25 25, 19.53125
Fibre Channel
FC1 1.0625 GHz
FC2 2.1250 GHz
106.25, 53.125, 132.8125 16.6015625, 25
Infi niband 2.5 GHz 125, 250 25
frequencies as well as the 8432I-101 configurations used to
generate the appropriate frequency.
Interconnect
Technology
CLK, nCLK Input
(MHz)
8432I-101
Output Frequency
to SERDES
(MHz)
8432I-101
M & N Settings
M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N0
Gigabit Ethernet
25 125 00001010010
25 250 00001010001
25 156.25 00001100110
19.53125 156.25 00010000010
Fiber Channel 1
25 53.125 00001000111
25 106.25 00001000110
Fiber Channel 2 16.6015625 132.8125 00010000010
Infi niband
25 125 00001010010
25 250 00001010001
