PIC16(L)F153XX
DS40001835A-page 12 Advance Information 2016 Microchip Technology Inc.
PIN ALLOCATION TABLES
TABLE 3: 8-PIN ALLOCATION TABLE (PIC16(L)F15313)
I/O
(2)
8-Pin PDIP/SOIC/
MSOP
ADC
Reference
Comparator
NCO
DAC
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RA0 7 ANA0 ― C1IN0+ ― DAC1OUT ― ― ― ― ― ― TX/CK
(1)
CLCIN3
(1)
― IOCA0 Y ICDDAT/
ICSPDAT
RA1 6 ANA1 V
REF+
C1IN0- ― DA1
REF+
T0CKI
(1)
―――SSP1CLK
(1),(4)
SSP1DAT
(1),(4)
― RX/DT
(1)
CLCIN2
(1)
― IOCA1 Y ICDCLK/
ICSPCLK
RA2 5 ANA2 V
REF-
― ― DAC1
REF-
― ― ― CWG1
(1)
SSP1CLK
(1),(4)
SSP1DAT
(1),(4)
ZCD1 ― ― ― INT
(1)
IOCA2
Y ―
RA3 4 ―――― ― ――――SSP1SS
(1)
――CLCIN0
(1)
― IOCA3 Y MCLR
V
PP
RA4 3 ANA4 ― C1IN1- ― ― T1G
(1)
SOSCO
― ― ― ― ― ― ― ― IOCA4 Y CLKOUT
OSC2
RA5 2 ANA5
ADACT
(1)
―― ― ―T1CKI
(1)
T2IN
(1)
SOSCIN
SOSCI
CCP1
(1)
CCP2
(1)
―― ― ――CLCIN1
(1)
― IOCA5 Y CLKIN
O S C 1
EIN
V
DD
1 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― V
DD
V
SS
8 ―――― ― ―――― ― ―― ―――― V
SS
OUT
(2)
―― ―C1OUT NCO1OUT ― TMR0 CCP1 PWM3 CWG1A SDO1 ―
DT1
(3)
CLC1OUT CLKR ―― ―
― ― ― C2OUT ― ― ― CCP2 PWM4 CWG1B SCK1 ― CK1 CLC2OUT ― ― ― ―
―― ―― ― ― ― ―PWM5 CWG1C SCL1
(3),(4)
― TX1 CLC3OUT ――――
― ― ― ― ― ― ― ― PWM6 CWG1D SDA1
(3),(4)
― ― CLC4OUT ― ― ― ―
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I
2
C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I
2
C
specific or SMBUS input buffer thresholds.
