PIC16(L)F153XX
DS40001835A-page 14 Advance Information 2016 Microchip Technology Inc.
RB6 ― ― 11 8 ANB6 ― ― ― ― ― ― ― ― SSP1CLK
(1),(6)
SSP1DAT
(1),(6)
― ― ― ― IOCB6 Y ―
RB7 ― ― 10 7 ANB7 ―― ― ― ― ― ― ― SSP2CLK
(1),(6)
SSP2DAT
(1),(6)
― TX1/CK1
(6)
――IOCB7 Y ―
V
DD
1 16 1 18 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― V
DD
V
SS
14 13 20 17 ―――― ― ――――― ―― ― ―――V
SS
OUT
(2)
――――― ― C1OUT NCO1OUT ― TMR0 CCP1 PWM3 CWG1A SDO1
SDO2
― DT1
(3)
CLC1OUT CLKR ―――
― ― ― ― ― ― C2OUT ― ― ― CCP2 PWM4 CWG1B SCK1
SCK2
― CK1 CLC2OUT ― ― ― ―
――――― ― ― ― ― ― ― PWM5 CWG1C SCL1
(3),(4)
SCL2
(3),(4)
― TX1 CLC3OUT ―― ――
― ― ― ― ― ― ― ― ― ― ― PWM6 CWG1D SDA1
(3),(4)
SDA2
(3),(4)
― ― CLC4OUT ― ― ― ―
Note 1: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2: All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I
2
C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I
2
C specific or
SMBUS input buffer thresholds.
5: For 14 and 16-pin package only.
6: For 20-pin package only.
TABLE 4: 14/16/20-PIN ALLOCATION TABLE (PIC16(L)F15323, PIC16(L)F15324, PIC16(L)F15325, PIC16(L)F15344, PIC16(L)F15345)
I/O
(2)
14-Pin PDIP/SOIC/TSSOP
16-Pin QFN/UQFN
20-Pin PDIP/SOIC/SSOP
20-Pin QFN
ADC
Reference
Comparator
NCO
DAC
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
