PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
10 ©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
Table 12: IDD Specifications and Conditions – 256MB
Values are shown for the MT46V32M16 DDR SDRAM only and are computed from values specified in the
512Mb (32 Meg x 16) component data sheet
Parameter/Condition Symbol -40B -335 -265 Units
Operating one bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
IDD0 775 650 575 mA
Operating one bank active-read-precharge current: BL = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD1 975 800 725 mA
Precharge power-down standby current: All device banks idle; Power-
down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD2P 25 25 25 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other control inputs
changing once per clock
cycle; V
IN
=V
REF
for DQ, DQS, and DM
IDD2F 275 225 200 mA
Active power-down standby current: One device bank active; Power-
down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD3P 225 175 150 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
IDD3N 300 250 225 mA
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle;
t
CK =
t
CK (MIN); IOUT =0mA
IDD4R 1,050 825 725 mA
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle
IDD4W 1,075 975 675 mA
Auto refresh current
t
REFC =
t
RFC (MIN)
IDD5 1,725 1,450 1,400 mA
t
REFC = 7.8125µs
IDD5A 55 50 50 mA
Self refresh current: CKE ≤ 0.2V
IDD6302525mA
Operating bank interleave read current: Four device bank interleaving
reads; BL = 4 with auto precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN);
Address and control inputs change only during active READ or WRITE
commands
IDD7 2,400 2,025 1,750 mA
