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MT5VDDT1672AY-335K1

P1-P3P4-P6P7-P9P10-P12
PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
7 ©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 8 may cause permanent damage to the
module. This is a stress rating only, and functional operation of the module at these or
any other conditions outside those indicated on the device data sheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may adversely
affect reliability.
Notes: 1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available
on Micron’s Web site.
Input Capacitance
Micron encourages designers to simulate the performance of the module to achieve
optimum values. Simulations are significantly more accurate and realistic than a gross
estimation of module capacitance when inductance and delay parameters associated
with trace lengths are used in simulations. JEDEC modules are currently designed using
simulations to close timing budgets.
Component AC Timing and Operating Conditions
Recommended AC operating conditions are given in the DDR component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades
correlate with component speed grades, as shown in Table 9.
Table 8: Absolute Maximum Ratings
Symbol Parameter Min Max Units
V
DD/VDDQ
VDD/VDDQ supply voltage relative to VSS
–1.0 +3.6 V
V
IN, VOUT
Voltage on any pin relative to VSS
–0.5 +3.2 V
I
I
Input leakage current; Any input 0V ≤ VIN ≤ VDD;
V
REF input 0V ≤ VIN ≤ 1.35V (All other pins not under
test = 0V)
Address inputs,
RAS#, CAS#, WE#, BA,
S#, CKE
–10 +10 µA
CK0, CK0#
–2 +2
CK1, CK1#, CK2, CK2#
–4 +4
DM
–2 +2
I
OZ
Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ are
disabled
DQ, DQS
–5 +5 µA
T
A
DRAM ambient operating temperature
1
Commercial
0+70°C
Industrial
–40 +85 °C
Table 9: Module and Component Speed Grades
Module Speed Grade Component Speed Grade
-40B -5B
-335 -6
-262 -75E
-26A -75Z
-265 -75
PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
8 ©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
IDD Specifications
Table 10: IDD Specifications and Conditions – 64MB
Values are shown for the MT46V8M16 DDR SDRAM only and are computed from values specified in the
128Mb (8 Meg x 16) component data sheet
Parameter/Condition Symbol -335 -262
-26A/
-265 Units
Operating one bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
IDD0 625 575 550 mA
Operating one bank active-read-precharge current: BL = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD1 675 675 625 mA
Precharge power-down standby current: All device banks idle; Power-
down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD2P 15 15 15 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other control inputs
changing once per clock cycle;
V
IN
=V
REF
for DQ, DQS, and DM
IDD2F 225 225 200 mA
Active power-down standby current: One device bank active; Power-
down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD3P 125 125 100 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice
per clock cycle; Address and other control inputs changing once per clock
cycle
IDD3N 250 250 225 mA
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); IOUT =0mA
IDD4R 725 700 675 mA
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle
IDD4W 775 675 650 mA
Auto refresh current
t
REFC =
t
RFC (MIN)
IDD5 1,325 1,250 1,250 mA
t
REFC = 15.625µs
IDD5A 25 25 25 mA
Self refresh current: CKE ≤ 0.2V
IDD6151510mA
Operating bank interleave read current: Four device bank interleaving
reads; BL = 4 with auto precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address
and control inputs change only during active READ or WRITE commands
IDD7 1,925 1,875 1,875 mA
PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
9 ©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
Table 11: IDD Specifications and Conditions – 128MB
Values are shown for the MT46V16M16 DDR SDRAM only and are computed from values specified in the
256Mb (16 Meg x 16) component data sheet
Parameter/Condition Symbol -40B -335 -262
-26A/
-265
Units
Operating one bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two clock cycles
IDD0 675 625 625 600 mA
Operating one bank active-read-precharge current: BL = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); IOUT = 0mA; Address and control
inputs changing once per clock cycle
IDD1 925 900 850 775 mA
Precharge power-down standby current: All device banks idle;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD2P 20 20 20 20 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle; V
IN
=V
REF
for DQ, DQS, and DM
IDD2F 300 250 225 225 mA
Active power-down standby current: One device bank active;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD3P 200 150 125 125 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
IDD3N 350 300 250 250 mA
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle;
t
CK =
t
CK (MIN); IOUT =0mA
IDD4R 1,300 1,100 925 925 mA
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per
clock cycle
IDD4W 1,075 975 800 800 mA
Auto refresh current
t
REFC =
t
RFC (MIN)
IDD5 1,300 1,275 1,175 1,175 mA
t
REFC = 7.8125µs
IDD5A 30 30 30 30 mA
Self refresh current: CKE ≤ 0.2V
IDD620202020mA
Operating bank interleave read current: Four device bank
interleaving reads; BL = 4 with auto precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control inputs change only during active
READ or WRITE commands
IDD7 2,550 2,200 1,900 1,900 mA
P1-P3P4-P6P7-P9P10-P12

MT5VDDT1672AY-335K1

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Manufacturer:
Micron
Description:
MODULE DDR SDRAM 128MB 184UDIMM
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