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7134SA55JG8

P1-P3P4-P6P7-P9P10-P12
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,2)
(VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part number indicates power rating (SA or LA).
2. V
CC = 5V, TA = +25°C for typical, and parameters are not production tested.
3. f
MAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3.
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE = V
IL
Outputs Disabled
f = f
MAX
(3 )
COM'L SA
LA
140
140
240
200
140
140
240
200
140
140
240
200
mA
MIL &
IND
SA
LA
140
140
280
240
140
140
270
220
140
140
270
220
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and CE
R
= V
IH
f = f
MAX
(3 )
COM'L SA
LA
25
25
70
40
25
25
70
40
25
25
70
40
mA
MIL &
IND
SA
LA
25
25
70
50
25
25
70
50
25
25
70
50
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
Active Port Outputs Disabled,
f=f
MAX
(3)
COM'L SA
LA
75
75
160
130
75
75
160
130
75
75
160
130
mA
MIL &
IND
SA
LA
75
75
190
150
75
75
180
150
75
75
180
150
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(3)
COM'L SA
LA
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
mA
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CE
"A"
or
CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(3 )
COM'L SA
LA
75
75
150
100
75
75
150
100
75
75
150
100
mA
MIL &
IND
SA
LA
75
75
180
120
75
75
170
120
75
75
170
120
2720 tbl 06b
7134X20
Com'l Only
7134X25
Com'l & Ind
7134X35
Com'l
& Military
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE = V
IL
Outputs Disabled
f = f
MAX
(3)
COM'L SA
LA
170
170
280
240
160
160
280
220
150
150
260
210
mA
MIL &
IND
SA
LA
____
____
____
____
160
160
310
260
150
150
300
250
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and CE
R
= V
IH
f = f
MAX
(3)
COM'L SA
LA
25
25
100
80
25
25
80
50
25
25
75
45
mA
MIL &
IND
SA
LA
____
____
____
____
25
25
100
80
25
25
75
55
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
Active Port Outputs Disabled,
f=f
MAX
(3)
COM'L SA
LA
105
105
180
150
95
95
180
140
85
85
170
130
mA
MIL &
IND
SA
LA
____
____
____
____
95
95
210
170
85
85
200
160
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(3)
COM'L SA
LA
1.0
0.2
15
4.5
1.0
0.2
15
4.0
1.0
0.2
15
4.0
mA
MIL &
IND
SA
LA
____
____
____
____
1.0
0.2
30
10
1.0
0.2
30
10
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CE
"A"
or
CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(3)
COM'L SA
LA
105
105
170
130
95
95
170
120
85
85
160
11 0
mA
MIL &
IND
SA
LA
____
____
____
____
95
95
210
150
85
85
190
130
2720 tbl 06a
5
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
V
CC
CE
DA
T
ARE
T
EN
T
ION MODE
4.5V4.5V
V
DR
≥ 2V
V
DR
V
IH
V
IH
t
CDR
t
R
2720 drw 05
Data Retention Characteristics Over All Temperature Ranges
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Data Retention Waveform
AC Test Conditions
Figure 1. AC Output Test Load Figure 2. Output Test Load
(for t
LZ, tHZ, tWZ, tOW)
*Including scope and jig
+5V
1250Ω
30pF
775Ω
DATA
OUT
2720 drw 06
,
+5V
1250Ω
5pF *
775Ω
DATA
OUT
2720 drw 07
,
NOTES:
1. V
CC = 2V, TA = +25°C, and are not production tested.
2. t
RC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but not production tested.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1 and 2
2720 tbl 08
Symbol Parameter Test Condition Min. Typ.
(1 )
Max. Unit
V
DR
V
CC
for Data Retention V
CC
= 2V 2.0
___ ___
V
I
CCDR
Data Retention Current
CE >
V
HC
V
IN
> V
HC
or < V
LC
MIL. & IND.
___
100 4000
µA
COM'L.
___
100 1500
t
CD R
(3 )
Chip Deselect to Data Retention Time 0
___ ___
ns
t
R
(3 )
Operation Recovery Time t
RC
(2 )
___ ___
ns
2720 tbl 07
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
6
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (SA or LA).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(3)
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 45
____
55
____
70
____
ns
t
AA
Address Access Time
____
45
____
55
____
70 ns
t
ACE
Chip Enable Access Time
____
45
____
55
____
70 ns
t
AOE
Output Enable Access Time
____
25
____
30
____
40 ns
t
OH
Output Hold from Address Change 0
____
0
____
0
____
ns
t
LZ
Output Low-Z Time
(1,2)
5
____
5
____
5
____
ns
t
HZ
Output High-Z Time
(1,2)
____
20
____
25
____
30 ns
t
PU
Chip Enable to Power Up Time
(2 )
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
45
____
50
____
50 ns
2720 tbl 09b
7134X20
Com'l Only
7134X25
Com'l & Ind
7134X35
Com'l
& Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 20
____
25
____
35
____
ns
t
AA
Address Access Time
____
20
____
25
____
35 ns
t
ACE
Chip Enable Access Time
____
20
____
25
____
35 ns
t
AOE
Output Enable Access Time
____
15
____
15
____
20 ns
t
OH
Output Hold from Address Change 0
____
0
____
0
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
15
____
20 ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
20
____
25
____
35 ns
2720 tbl 09a
P1-P3P4-P6P7-P9P10-P12

7134SA55JG8

Mfr. #:
Buy 7134SA55JG8
Manufacturer:
IDT
Description:
SRAM 32K(2KX16)CMOS DUAL PORT
Lifecycle:
New from this manufacturer.
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