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7134SA55JG8

P1-P3P4-P6P7-P9P10-P12
7
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side
(1,2,4)
Timing Waveform of Read Cycle No. 2, Either Side
(1,3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = V
IH.
4. Start of valid data depends on which timing becomes effective, t
AOE, tACE or tAA
5. tAA for RAM Address Access and tSAA for Semaphore Address Access.
ADDRESS
DATA
OUT
PREVIOUS DATA VALID DATA VALID
t
OH
t
OH
t
AA
(5)
t
RC
2720 drw 08
2720 drw 09
CE
DATA
OUT
VALID DATA
(4)
t
PD
t
AOE
(4)
t
ACE
OE
t
HZ
(2)
t
LZ
(1)
t
LZ
(1)
t
PU
50%50%
I
CC
I
SB
CURRENT
t
HZ
(2)
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for t
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual t
DH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. 'X' in part number indicates power rating (SA or LA).
Symbol Parameter
7134X20
Com'l Only
7134X25
Com'l & Ind
7134X35
Com'l
& Military
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 20
____
25
____
35
____
ns
t
EW
Chip Enable to End-of-Write 15
____
20
____
30
____
ns
t
AW
Address Valid to End-of-Write 15
____
20
____
30
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Pulse Width 15
____
20
____
25
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
15
____
20
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
15
____
20 ns
t
DH
Data Hold Time
(3)
0
____
0
____
3
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
15
____
20 ns
t
OW
Output Active from End-of-Write
(1,2,3)
3
____
3
____
3
____
ns
t
WDD
Write Pulse to Data Delay
(4)
____
40
____
50
____
60 ns
t
DDD
Write Data Valid to Read Data Delay
(4)
____
30
____
30
____
35 ns
2720 tbl 10a
Symbol Parameter
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 45
____
55
____
70
____
ns
t
EW
Chip Enable to End-of-Write 40
____
50
____
60
____
ns
t
AW
Address Valid to End-of-Write 40
____
50
____
60
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Pulse Width 40
____
50
____
60
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 20
____
25
____
30
____
ns
t
HZ
Output High-Z Time
(1,2)
____
20
____
25
____
30 ns
t
DH
Data Hold Time
(3)
3
____
3
____
3
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
20
____
25
____
30 ns
t
OW
Output Active from End-of-Write
(1,2,3)
3
____
3
____
3
____
ns
t
WDD
Write Pulse to Data Delay
(4)
____
70
____
80
____
90 ns
t
DDD
Write Data Valid to Read Data Delay
(4)
____
45
____
55
____
70 ns
2720 tbl 10b
9
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
2720 drw 10
R/W
"A"
(1)
VALID
t
WC
MATCH
VALID
MATCH
t
WP
t
DW
t
WDD
t
DDD
ADDR
"A"
DATA
IN "A"
DATA
OUT "B"
ADDR
"B"
t
AW
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
Timing Waveform of Write with Port-to-Port Read
(1,2,3)
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CE
L = CER = VIL. OE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a CE =VIL and R/W = VIL.
3. t
WR is measured from the earlier of CE or R/W going to VIH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE = V
IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = V
IL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus
for the required t
DW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
CE
2720 drw 11
t
AW
t
AS
(6)
t
DW
DATA
IN
ADDRESS
t
WC
R/W
t
WP
DATA
OUT
t
WZ
(7)
(4)
(4)
(2)
OE
t
HZ
(7)
t
LZ
(7)
t
HZ
t
WR
(3)
(7)
t
DH
t
OW
P1-P3P4-P6P7-P9P10-P12

7134SA55JG8

Mfr. #:
Buy 7134SA55JG8
Manufacturer:
IDT
Description:
SRAM 32K(2KX16)CMOS DUAL PORT
Lifecycle:
New from this manufacturer.
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