18
LTC3737
3737fa
APPLICATIO S I FOR ATIO
WUUU
If the external clock frequency is greater than the internal
oscillator’s frequency, f
OSC
, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f
OSC
, current is sunk continuously, pulling down the
PLLLPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage on the PLLLPF pin is adjusted until
the phase and frequency of the internal and external
oscillators are identical. At the stable operating point, the
phase detector output is high impedance and the filter
capacitor C
LP
holds the voltage.
The loop filter components, C
LP
and R
LP
, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
= 10k and C
LP
is 2200pF to
0.01µF.
Typically, the external clock (on the SYNC/MODE pin)
input high level is 1.6V, while the input low level is 1.2V.
These levels are guaranteed to be TTL/CMOS compatible:
0.8V is guaranteed low, while 2.0V is guaranteed high.
Table 1 summarizes the different states in which the
PLLLPF pin can be used.
Table 1
PLLLPF PIN SYNC/MODE PIN FREQUENCY
0V DC Voltage 300kHz
Floating DC Voltage 550kHz
V
IN
DC Voltage 750kHz
RC Loop Filter Clock Signal Phase-Locked to External Clock
Fault Condition: Short Circuit and Current Limit
To prevent excessive heating of the catch diode, foldback
current limiting can be added to reduce the current in
proportion to the severity of the fault.
Foldback current limiting is implemented by adding di-
odes D
FB1
and D
FB2
between the output and the I
TH
pin as
shown in Figure 11. In a hard short (V
OUT
= 0V), the current
will be reduced to approximately 50% of the maximum
output current.
Low Supply Operation
Although the LTC3737 can function down to below 2.4V,
the maximum allowable output current is reduced as V
IN
decreases below 3V. Figure 12 shows the amount of
change as the supply is reduced down to 2.4V. Also shown
is the effect on V
REF
.
Figure 12. Line Regulation of V
REF
and Maximum Sense Voltage
INPUT VOLTAGE (V)
75
NORMALIZED VOLTAGE OR CURRENT (%)
85
95
105
80
90
100
2.2 2.4 2.6 2.8
3737 F12
3.02.12.0 2.3 2.5 2.7 2.9
V
REF
MAXIMUM
SENSE VOLTAGE
Figure 11. Foldback Current Limiting
+
1/2 LTC3737
V
FB
I
TH
R2
D
FB1
V
OUT
D
FB2
3737 F11
R1
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
,
is the smallest amount of time
that the LTC3737 is capable of turning the top P-channel
MOSFET on and then off. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. The minimum on-time for the LTC3737 is
typically about 280ns. Low duty cycle and high frequency
applications may approach the minimum on-time limit
and care should be taken to ensure that:
t
VV
fVV
ON MIN
OUT D
OSC IN D
()
•
<
+
+
()
