7
LTC3737
3737fa
PGATE1
PGND
I
TH1
0.68V
0.12V
V
IN
OV1
PGOOD1
I
TH1
I
TH2
DUPLICATE FOR SECOND CHANNEL
0.54V
V
FB1
SOFT-START
V
REF
= 0.6V
V
REF
= 0.6V
TRACKV
FB2
R2B R2A
V
OUT2
R
C
C
C
3737 BD
OV1
SLEEP1
SC1
+
+
+
+
+
SWITCHING
LOGIC AND
BLANKING
CIRCUIT
+
+
+
0.15V
BURSTDIS
0.3V
Q
CLK1
SLOPE1
M1
D1
L1
S
R
SENSE1
+
IPROG1 PV
IN1
SW1
V
IN
C
IN
V
IN
I
CMP
VOLTAGE
CONTROLLED
OSCILLATOR
UNDERVOLTAGE
LOCKOUT
0.7µA
t = 1ms
INTERNAL
SOFT-START
V
IN
VOLTAGE
REFERENCE
CLK1
SLOPE1
BURSTDIS
SLOPE2
PGOOD1
PGOOD2
UVSD
CLK2
SLOPE
COMP
PHASE
DETECTOR
SYNC/MODE
PLLLPF
RUN/SS
V
IN
PGOOD
UV
UVSD
CMSD
V
REF
0.6V
SGND
CLOCK DETECT
BURST DEFEAT
OVP
SCP
C
OUT
V
OUT1
C
SS
SOFT-
START
EXTSS
INTSS
R1A
R1B R
TRACKB
R
TRACKA
+
+
EAMP1
EAMP2
+
+
MUX
V
FB
FU CTIO AL DIAGRA
U
U
W
8
LTC3737
3737fa
OPERATIO
U
(Refer to Functional Diagram)
Main Control Loop
The LTC3737 uses a constant frequency, current mode
architecture with the two controller channels operating
180 degrees out of phase. During normal operation, each
external P-channel power MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the current comparator (I
CMP
) resets the latch. The
peak inductor current at which I
CMP
resets the RS latch is
determined by the voltage on the I
TH
pin, which is the
output of each error amplifier (EAMP). The V
FB
pin re-
ceives the output voltage feedback signal from an external
resistor divider. This feedback signal is compared to the
internal 0.6V reference voltage by the EAMP. When the
load current increases, it causes a slight decrease in V
FB
relative to the 0.6V reference, which in turn, causes the I
TH
voltage to increase until the average inductor current
matches the new load current.
Shutdown, Soft-Start and Tracking Start-Up
(RUN/SS and TRACK Pins)
The LTC3737 is shut down by pulling the RUN/SS pin low.
In shutdown, all controller functions are disabled and the
chip draws only 9µA. The PGATE outputs are held high
(off) in shutdown. Releasing RUN/SS allows an internal
0.7µA current source to charge up the RUN/SS pin. When
the RUN/SS pin reaches 0.65V, the LTC3737’s two con-
trollers are enabled.
The start-up of V
OUT1
is controlled by the LTC3737’s
internal soft-start. During soft-start, the error amplifier
EAMP compares the feedback signal V
FB1
to the internal
soft-start ramp (instead of the 0.6V reference), which rises
linearly from 0V to 0.6V in about 1ms. This allows the
output voltage to rise smoothly from 0V to its final value,
while maintaining control of the inductor current.
The 1ms soft-start time can be increased by connecting
the optional external soft-start capacitor, C
SS
, between the
RUN/SS and SGND pins. As the RUN/SS pin continues to
rise linearly from approximately 0.65V to 1.3V (being
charged by the internal 0.7µA current source), the EAMP
regulates V
FB1
linearly from 0V to 0.6V.
The start-up of V
OUT2
is controlled by the voltage on the
TRACK pin. When the voltage on the TRACK pin is less
than the 0.6V internal reference, the LTC3737 regulates
the V
FB2
voltage to the TRACK pin instead of the 0.6V
reference. Typically, a resistor divider on V
OUT1
is con-
nected to the TRACK pin to allow the start-up of V
OUT2
to
“track” that of V
OUT1
. For one-to-one tracking during start-
up, the resistor divider would have the same values as the
divider on V
OUT2
that is connected to V
FB2
.
If no tracking function is desired, then the TRACK pin can
be tied to V
IN
. Note, however, that in this situation, there
would be no (internal or external) soft-start on V
OUT2
.
Light Load Operation (Burst Mode Operation or Pulse
Skipping Mode) (SYNC/MODE Pin)
The LTC3737 can be enabled to enter high efficiency Burst
Mode operation at low load currents. To select Burst Mode
operation, tie the SYNC/MODE pin to a DC voltage above
0.6V (e.g., V
IN
). To disable Burst Mode operation and
enable PWM pulse skipping mode, connect SYNC/MODE
to a DC voltage below 0.6V (e.g., SGND). In this mode, the
efficiency is lower at light loads. However, pulse skipping
mode has the advantages of lower output ripple and less
interference to audio circuitry.
When a controller is in Burst Mode operation, the peak
current in the inductor is set to approximate one-fourth of
the maximum sense voltage even when the voltage on the
I
TH
pin indicates a lower value. If the average inductor
current is greater than the load current, the EAMP will
decrease the voltage on the I
TH
pin. When the I
TH
voltage
drops below 0.85V, the internal SLEEP signal goes high
and the external MOSFET is turned off.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3737 draws.
The load current is supplied by the output capacitor. As the
output voltage decreases, the EAMP increases the I
TH
voltage. When the I
TH
voltage reaches 0.925V, the SLEEP
signal goes low and the controller resumes normal opera-
tion by turning on the external P-channel MOSFET on the
next cycle of the internal oscillator.
When the SYNC/MODE pin is clocked by an external clock
source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop), the LTC3737 operates
in PWM pulse skipping mode at light loads.
9
LTC3737
3737fa
OPERATIO
U
(Refer to Functional Diagram)
When a controller is in pulse skipping operation, an
internal offset at the current comparator input will assure
that the current comparator remains tripped even at zero
load current and the regulator will start to skip cycles, as
it must, in order to maintain regulation.
Short-Circuit Protection
When one of the outputs is shorted to ground (V
FB
<
0.12V), the switching frequency of that controller is re-
duced to 1/3 of the normal operating frequency. The other
controller is unaffected and maintains normal operation.
The short-circuit threshold on V
FB2
is based on the
smaller of 0.12V and a fraction of the voltage on the
TRACK pin. This also allows V
OUT2
to start up and track
V
OUT1
more easily. Note that if V
OUT1
is truly short
circuited (V
OUT1
= V
FB1
= 0V), then the LTC3737 will try to
regulate V
OUT2
to 0V if a resistor divider on V
OUT1
is
connected to the TRACK pin.
Output Overvoltage Protection
As a further protection, the overvoltage comparator (OVP)
guards against transient overshoots, as well as other more
serious conditions, that may overvoltage the output. When
the feedback voltage on the V
FB
pin has risen 13.33%
above the reference voltage of 0.6V, the external P-chan-
nel MOSFET is turned off until the overvoltage is cleared.
Frequency Selection and Phase-Locked Loop (PLLLPF
and SYNC/MODE Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage.
The switching frequency of the LTC3737’s controllers can
be selected using the PLLLPF pin. If the SYNC/MODE pin
is not being driven by an external clock source, the PLLLPF
pin can be floated, tied to V
IN
or tied to SGND to select
550kHz, 750kHz or 300kHz, respectively.
A phase-locked loop (PLL) is available on the LTC3737 to
synchronize the internal oscillator to an external clock
source that is connected to the SYNC/MODE pin. In this
case, a series RC should be connected between the
PLLLPF pin and SGND to serve as the PLL’s loop filter. The
LTC3737 phase detector adjusts the voltage on the PLLLPF
pin to align the turn-on of controller 1’s external P-channel
MOSFET to the rising edge of the synchronizing signal.
Thus, the turn-on of controller 2’s external P-channel
MOSFET is 180 degrees out of phase to the rising edge of
the external clock source.
The typical capture range of the LTC3737’s phase-locked
loop is from approximately 200kHz to 1MHz, with a
guarantee over all variations and temperature to be be-
tween 250kHz and 850kHz. In other words, the LTC3737’s
PLL is guaranteed to lock to an external clock source
whose frequency is between 250kHz and 850kHz.
Dropout Operation
When the input supply voltage (V
IN
) decreases towards
the output voltage, the rate of change of the inductor
current while the external P-channel MOSFET is on (ON
cycle) decreases. This reduction means that the P-channel
MOSFET will remain on for more than one oscillator cycle
if the inductor current has not ramped up to the threshold
set by the EAMP on the I
TH
pin. Further reduction in the
input supply voltage will eventually cause the P-channel
MOSFET to be turned on 100%; i.e., DC. The output
voltage will then be determined by the input voltage minus
the voltage drop across the P-channel MOSFET and the
inductor.
Undervoltage Lockout
To prevent operation of the P-channel MOSFET below safe
input voltage levels, an undervoltage lockout is incorpo-
rated in the LTC3737. When the input supply voltage (V
IN
)
drops below 2.25V, the external P-channel MOSFET and
all internal circuitry are turned off except for the undervolt-
age block, which draws only a few microamperes.

LTC3737EUF#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2-Phase Controller w/Tracking
Lifecycle:
New from this manufacturer.
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