10
Figure17.I
OH
testcircuit. Figure18.I
OL
testcircuit.
Figure19.V
OH
testcircuit. Figure20.V
OL
testcircuit.
Figure21.I
FLH
testcircuit. Figure22.UVLOtestcircuit.
0.1 µF
V
CC
= 10
to 20 V
1
3
I
F
= 10 to
16 mA
+
2
4
8
6
7
5
+
4 V/10
I
OH
0.1 µF
V
CC
= 10
to 20 V
1
3
+
2
4
8
6
7
5
2.5 V/10 V
I
OL
+
0.1 µF
V
CC
= 10
to 20 V
1
3
I
F
= 10 to
16 mA
+
2
4
8
6
7
5
100 mA
V
OH
0.1 µF
V
CC
= 10
to 20 V
1
3
+
2
4
8
6
7
5
100 mA
V
OL
0.1 µF
V
CC
= 10
to 20 V
1
3
I
F
+
2
4
8
6
7
5
V
O
> 5 V
0.1 µF
V
CC
1
3
I
F
= 10 mA
+
2
4
8
6
7
5
V
O
> 5 V
11
Figure25.RecommendedLEDdriveandapplicationcircuitforHCPL-3180.
Figure23.t
PLH
,t
PHL
,t
r
andt
f
testcircuitandwaveform.
Figure24.CMRtestcircuitandwaveform.
ApplicationsInformationEliminatingNegativeIGBTGate
Drive
To keep the IGBT firmly off, the HCPL-3180 has a very
low maximum V
OL
specification of 0.4 V. The HCPL-3180
realizes the very low V
OL
by using a DMOS transistor with
1 W (typical) on resistance in its pull down circuit. When
the HCPL-3180 is in the low state, the IGBT gate is shorted
to the emitter by R
g
+ 1 W. Minimizing R
g
and the lead
inductance from the HCPL-3180 to the IGBT gate and
emitter (possibly by mounting HCPL-3180 on a small PC
board directly above the IGBT) can eliminate the need for
negative IGBT gate drive in many applications as shown
in Figure 25. Care should be taken with such a PC board
design to avoid routing the IGBT collector or emitter
traces close to the HCPL-3180 input as this can result in
unwanted coupling of transient signals into the input of
HCPL-3180 and degrade performance.
(If the IGBT drain must be routed near the HCPL-3180
input, then the LED should be reverse biased when in the
off state to prevent the transient signals coupled from the
IGBT drain from turning on the HCPL-3180.)
0.1 µF
V
CC
= 20 V
10
1
3
I
F
= 10 to 16 mA
V
O
+
+
2
4
8
6
7
5
250 KHz
50% DUTY
CYCLE
500
10 nF
I
F
V
OUT
t
PHL
t
PLH
t
f
t
r
10%
50%
90%
0.1 µF
V
CC
= 20 V
1
3
I
F
V
O
+
+
2
4
8
6
7
5
A
+
B
V
CM
= 1500 V
5 V
V
CM
t
0 V
V
O
SWITCH AT B: I
F
= 0 mA
V
O
SWITCH AT A: I
F
= 10 mA
V
OL
V
OH
t
V
CM
δV
δt
=
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF
V
CC
= 15 V
1
3
+
2
4
8
6
7
5
270
+5 V
CONTROL
INPUT
Rg
Q1
Q2
74XXX
OPEN
COLLECTOR
12
SelectingtheGateResistor(R
g
)forHCPL-3180
Step1: Calculate R
g
minimum from the I
OL
peak specification. The IGBT and
R
g
in Figure 25 can be analyzed as a simple RC circuit with a voltage supplied
by the HCPL-3180.
The V
OL
value of 3 V in the previous equation is the V
OL
at the peak current of
2 A. (See Figure 6.)
Step2: Check the HCPL-3180 power dissipation and increase R
g
if necessary.
The HCPL-3180 total power dissipation (P
T
) is equal to the sum of the emitter
power (P
E
) and the output power (P
O
).
PT = PE + PO
PE = IF * VF * Duty Cycle
PO = PO(BIAS) + PO(SWITCHING)
= ICC * VCC + ESW (R
g
;Q
g
) * f
For the circuit in Figure 25 with IF (worst case) = 16 mA, R
g
= 10 Ω, Max Duty
Cycle = 80%, Q
g
= 100 nC, f = 200 kHz and T
AMAX
= +75°C:
PE = 16 mA * 1.8 V * 0.8 = 23 mW
PO = 4.5 mA * 20 V + 0.85 µ * 200 kHz
= 260 mW ≥ 226 mW (PO(MAX) @ 75°C = 250 mW (5°C * 4.8 mW/°C))
The value of 4.5 mA for I
CC
in the previous equation was obtained by derating
the I
CC
max of 6 mA to I
CC
max at +75°C. Since P
O
for this case is greater than
the P
O(MAX)
, R
g
must be increased to reduce the HCPL-3180 power dissipa-
tion.
PO(SWITCHING MAX) = PO(MAX) – PO(BIAS)
= 226 mW – 90 mW
= 136 mW
ESW(MAX) = PO(SWITCHING MAX)
f
= 136 mW
200 kHz
= 0.68 µW
For Q
g
= 100 nC, a value of E
sw
= 0.68 µW gives a R
g
= 15 W.
=
20 – 3
2
= 8.5 Ω
Figure26.EnergydissipatedintheHCPL-3180andfor
eachIGBT.
R
g
V
CC
V
OL
I
OLPEAK
E
sw
– ENERGY PER SWITCHING CYCLE – µJ
0
0
R
g
— GATE RESISTANCE —
50
0.6
10
2.0
1.4
1.6
1.8
20
0.4
30 40
1.2
Q
g
= 100 nC
1.0
0.8
0.2

HCPL-3180-360

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers 2.0A IGBT Gate Drive
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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